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| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 125/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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TI Extension Registers
194
September 2005
SCPS110
9.4
Link Enhancement Register
This register is a memory-mapped set/clear register that is an alias of the link enhancement control register
at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial
EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software,
then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset
50h/54h (see Section 8.16). See Table 93 for a complete description of the register contents.
TI extension register offset:
A88h
set register
A8Ch
clear register
Register type:
Read/Set/Clear, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
Table 93. Link Enhancement Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
RSVD
R
Reserved. Bits 3116 return 0000h when read.
15
dis_at_pipeline
RW
Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value for
this bit is 0b.
14
RSVD
R
Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.
1312
atx_thresh
RW
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the controller
retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is
optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus
latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or
when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT
threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun
condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a
store-and-forward operation. It waits until it has the complete packet in the FIFO before retransmitting it on
the second attempt to ensure delivery.
An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not
transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only
complete packets being transmitted.
Note that this controller always uses a store-and-forward operation when the asynchronous transmit retries
register at OHCI offset 08h (see Section 8.3) is cleared.
11
RSVD
R
Reserved. Bit 11 returns 0b when read.
10
enab_mpeg_ts
RW
Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for MPEG
CIP transmit streams (FMT = 20h). The default value for this bit is 0b.
9
RSVD
R
Reserved. Bit 9 returns 0b when read.
8
enab_dv_ts
RW
Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for DV CIP
transmit streams (FMT = 00h). The default value for this bit is 0b.
7
enab_unfair
RW
Enable asynchronous priority requests. OHCI-Lynx
compatible. Setting bit 7 to 1b enables the link to
respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The default value
for this bit is 0b.
This bit is cleared only by the assertion of GRST.
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