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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 251/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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Principles of Operation
64
September 2005
SCPS110
Table 314. Requirements for Internal/External 1.5-V Core Power Supply
SUPPLY
VCC
VR_EN
VR_PORT
NOTE
Internal
3.3 V
GND
1.5-V output
Internal 1.5-V LDO-VR is enabled. A 1.0-
F bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External
3.3 V
VCC
1.5-V input
Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-
F bypass capacitor on the VR_PORT terminal is required.
3.8.3 Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCIxx12
controller. CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not
implement CLKRUN, this is not always available to the system designer, and alternate power-saving features
are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide.
The controller does not permit the central resource to stop the PCI clock under any of the following conditions:
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The 16-bit PC Card resource manager is busy.
The PCIxx12 CardBus master state machine is busy. A cycle may be in progress on CardBus.
The PCIxx12 master is busy. There may be posted data from CardBus, 1394, flash media core, SD host
core, or Smart Card core to PCI in the controller or DMA is active.
Interrupts are pending from CardBus, 1394, flash media core, SD host core, or Smart Card core
The CardBus CCLK for the socket has not been stopped by the PCIxx12 CCLKRUN manager.
Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.23) is set.
The 1394 resource manager is busy.
The PCIxx12 1394 master state machine is busy. A cycle may be in progress on 1394.
PC Card interrogation is in progress.
Flash media or Smart Card insertion/removal processing
The 1394 bus is not idle.
Smart card DES request or decryption in progress
The controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
A 1394 device changes the status of the twisted pair lines from idle to active.
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
Data is in any of the FIFOs (receive or transmit).
The master state machine is busy.
There are pending interrupts from CardBus, 1394, flash media core, SD host core, or Smart Card core.
3.8.4 CardBus PC Card Power Management
The PCIxx12 controller implements its own card power-management engine that can turn off the CCLK to a
socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the
CardBus CCLKRUN interface to control this clock management.
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