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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 266/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SNA7412ZHK |
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PC Card Controller Programming Model
78
September 2005
SCPS110
4.4
Command Register
The PCI command register provides control over the PCIxx12 interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification (see Table 43). None of the bit functions in this register
are shared among the PCIxx12 PCI functions. Five command registers exist in the controller, one for each
function. Software manipulates the functions as separate entities when enabling functionality through the
command register. The SERR_EN and PERR_EN enable bits in this register are internally-wired OR between
the five functions, and these control bits appear to software to be separate for each function.
PCI register offset:
04h
Register type:
Read-only, Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 43. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
Reserved. Bits 1511 return 00000b when read.
10
INT_DISABLE
RW
INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9
FBB_EN
R
Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, this
bit is read-only. This bit returns a 0b when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the controller to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
RSVD
R
Reserved. Bit 7 returns 0b when read.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCIxx12 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
0 = Controller ignores detected parity errors (default)
1 = Controller responds to detected parity errors
5
VGA_EN
RW
VGA palette snoop. When set to 1b, palette snooping is enabled (i.e., the controller does not respond to
palette register writes and snoops the data). When the bit is 0b, the controller treats all palette accesses
like all other accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The controller does not support memory write-and-invalidate commands,
it uses memory write commands instead; therefore, this bit is hardwired to 0b. This bit returns 0b when
read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The controller does
not respond to special cycle operations; therefore, this bit is hardwired to 0b. This bit returns 0b when read.
Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the controller can act as a PCI bus initiator (master).
The controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCIxx12 ability to generate PCI bus accesses (default)
1 = Enables the PCIxx12 ability to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. This bit controls whether or not the controller can claim cycles in PCI memory
space.
0 = Disables the PCIxx12 response to memory space accesses (default)
1 = Enables the PCIxx12 response to memory space accesses
0
IO_EN
RW
I/O space control. This bit controls whether or not the controller can claim cycles in PCI I/O space.
0 = Disables the controller from responding to I/O space accesses (default)
1 = Enables the controller to respond to I/O space accesses
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