
Flash Media Controller Programming Model
203
September 2005
SCPS110
11
Flash Media Controller Programming Model
This section describes the internal PCI configuration registers used to program the the PCI6412, PCI6612,
PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 flash media controller interface. All registers are
detailed in the same format: a brief description for each register is followed by the register offset and a bit table
describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose,
indicates bit field names, a detailed field description, and field access tags which appear in the type column.
Table 41 describes the field access tags.
The controller is a multifunction PCI device. The flash media controller core is integrated as PCI function 2.
The function 2 configuration header is compliant with the PCI Local Bus Specification as a standard header.
Table 111 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 111. Function 2 Configuration Register Map
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Latency timer
Cache line size
0Ch
Flash media base address
10h
Reserved
14h28h
Subsystem ID
Subsystem vendor ID
2Ch
Reserved
30h
Reserved
PCI
power-management
capabilities pointer
34h
Reserved
38h
Maximum latency
Minimum grant
Interrupt pin
Interrupt line
3Ch
Reserved
40h
Power-management capabilities
Next item pointer
Capability ID
44h
PM data
(Reserved)
PMCSR_BSE
Power-management control and status
48h
Reserved
General control
4Ch
Subsystem access
50h
Diagnostic
54h
Reserved
58hFCh
One or more bits in this register are cleared only by the assertion of GRST.
11.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI
device. The vendor ID assigned to Texas Instruments is 104Ch.
Function 2 offset:
00h
Register type:
Read-only
Default value:
104Ch
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
1
0