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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 246/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SNA7412ZHK |
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Principles of Operation
60
September 2005
SCPS110
The naming convention for PC Card signals describes the function for CardBus, 16-bit memory, and 16-bit
I/O cards. For example, CINT//READY(IREQ) includes CINT for CardBus cards, READY for 16-bit memory
cards, and IREQ for 16-bit I/O cards. The CardBus signal name is first. The 16-bit memory card signal name
follows after a double slash (//) with the 16-bit I/O card signal name second, enclosed in parentheses.
The 1997 PC Card Standard describes the power-up sequence that must be followed by the controller when
an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion
of this power-up sequence, the PCIxx12 interrupt scheme can be used to notify the host system (see
Table 311), denoted by the power cycle complete event. This interrupt source is considered a PCIxx12
internal event, because it depends on the completion of applying power to the socket rather than on a signal
change at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 311
by setting the appropriate bits in the PCIxx12 controller. By individually masking the interrupt sources listed,
software can control those events that cause a PCIxx12 interrupt. Host software has some control over the
system interrupt the controller asserts by programming the appropriate routing registers. The controller allows
host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt
routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following
sections.
When an interrupt is signaled by the controller, the interrupt service routine must determine which of the events
listed in Table 310 caused the interrupt. Internal registers in the controller provide flags that report the source
of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.
Table 310 details the registers and bits associated with masking and reporting potential interrupts. All
interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available
for all types of interrupts.
Notice that there is not a mask bit to stop the controller from passing PC Card functional interrupts through
to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there
must never be a card interrupt that does not require service after proper initialization.
Table 310 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit
PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write
of 1b to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing
methods is made by bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see
Section 5.20), and defaults to the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1b to the interrupt flag in the socket
event register (see Section 6.1). Although some of the functionality is shared between the CardBus registers
and the ExCA registers, software must not program the chip through both register sets when a CardBus card
is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6MFUNC0, implemented in the PCIxx12 controller can be routed
to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions.
To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI
offset 92h, see Section 4.38), to select the parallel IRQ signaling scheme. See Section 4.35, Multifunction
Routing Status Register, for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This
requirement is dictated by certain card and socket-services software. The INTA requirement calls for routing
the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket interrupt events
to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
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