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| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 106/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SNA7412ZHK |
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OHCI Registers
178
September 2005
SCPS110
8.33 PHY Layer Control Register
The PHY layer control register reads from or writes to a PHY register. See Table 825 for a complete
description of the register contents.
OHCI register offset:
ECh
Register type:
Read/Write/Update, Read/Write, Read/Update, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 825. PHY Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
rdDone
RU
Bit 31 is cleared to 0b by the controller when either bit 15 (rdReg) or bit 14 (wrReg) is set to 1b. This
bit is set to 1b when a register transfer is received from the PHY layer.
3028
RSVD
R
Reserved. Bits 3028 return 000b when read.
2724
rdAddr
RU
This field is the address of the register most recently received from the PHY layer.
2316
rdData
RU
This field is the contents of a PHY register that has been read.
15
rdReg
RWU
Bit 15 is set to 1b by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1b
simultaneously.
14
wrReg
RWU
Bit 14 is set to 1b by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1b
simultaneously.
1312
RSVD
R
Reserved. Bits 13 and 12 return 00b when read.
118
regAddr
RW
This field is the address of the PHY register to be written or read. The default value for this field is 0h.
70
wrData
RW
This field is the data to be written to a PHY register and is ignored for reads. The default value for this
field is 00h.
8.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the controller is
cycle master, this register is transmitted with the cycle start message. When the controller is not cycle master,
this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message
is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time
reference. See Table 826 for a complete description of the register contents.
OHCI register offset:
F0h
Register type:
Read/Write/Update
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
Table 826. Isochronous Cycle Timer Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3125
cycleSeconds
RWU
This field counts seconds [rollovers from bits 2412 (cycleCount field)] modulo 128.
2412
cycleCount
RWU
This field counts cycles [rollovers from bits 110 (cycleOffset field)] modulo 8000.
110
cycleOffset
RWU
This field counts 24.576-MHz clocks modulo 3072, that is, 125
s. If an external 8-kHz clock
configuration is being used, then this field must be cleared to 000h at each tick of the external clock.
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