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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 231/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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Principles of Operation
46
September 2005
SCPS110
In addition to loading configuration data from an EEPROM, the I2C bus can be used to read and write from
other I2C serial devices. A system designer can control the I2C bus, using the controller as bus master, by
reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status
register (PCI offset B3h, see Section 4.49) causes the controller to route the SDA and SCL signals to the SDA
and SCL terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by
accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h,
and B2h; see Sections 4.46, 4.47, and 4.48, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI
offset B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the serial ROM
circuitry detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results
in bit 0 (ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM
interface is busy).
The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes
to all four functions from the serial EEPROM loader.
SCL
SDA
VCC
A0
A1
A2
SCL
SDA
PCIxx12
Serial
ROM
Figure 34. Serial ROM Application
3.4.4 Function 0 (CardBus) Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset
42h, see Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword
register is used for system and option card (mobile dock) identification purposes and is required by some
operating systems. Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The PCIxx12 controller offers two mechanisms to load a read-only value into the subsystem registers. The
first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to
the subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system
control register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem
identification value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the
subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves
the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the
serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the
entire PCIxx12 core, including the serial-bus state machine (see Section 3.8.6, Suspend Mode, for details on
using SUSPEND).
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