
Electrical Characteristics
245
September 2005
SCPS110
14.4.2
Driver
PARAMETER
TEST CONDITION
MIN
MAX
UNIT
VOD
Differential output voltage
56
, See Figure 141
172
265
mV
IDIFF
Driver difference current, TPA+, TPA, TPB+, TPB
Drivers enabled, speed signaling off
1.05
mA
ISP200
Common-mode speed signaling current, TPB+, TPB
S200 speed signaling enabled
4.84
2.53
mA
ISP400
Common-mode speed signaling current, TPB+, TPB
S400 speed signaling enabled
12.4
8.10
mA
VOFF
Off state differential voltage
Drivers disabled, See Figure 141
20
mV
Limits defined as algebraic sum of TPA+ and TPA driver currents. Limits also apply to TPB+ and TPB algebraic sum of driver currents.
Limits defined as absolute limit of each of TPB+ and TPB driver currents.
TPAx+
TPBx+
TPAx
TPBx
56
Figure 141. Test Load Diagram
14.4.3
Receiver
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ZID
Differential impedance
Drivers disabled
4
7
k
ZID
Differential impedance
Drivers disabled
4
pF
ZIC
Common-mode impedance
Drivers disabled
20
k
ZIC
Common-mode impedance
Drivers disabled
24
pF
VTHR
Receiver input threshold voltage
Drivers disabled
30
mV
VTHCB
Cable bias detect threshold, TPBx cable inputs
Drivers disabled
0.6
1.0
V
VTH+
Positive arbitration comparator threshold voltage
Drivers disabled
89
168
mV
VTH
Negative arbitration comparator threshold voltage
Drivers disabled
168
89
mV
VTHSP200
Speed signal threshold
TPBIASTPA common mode
voltage, drivers disabled
49
131
mV
VTHSP400
Speed signal threshold
TPBIASTPA common mode
voltage, drivers disabled
314
396
mV
14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tc
Cycle time, PCLK
tcyc
30
ns
tw(H)
Pulse duration (width), PCLK high
thigh
11
ns
tw(L)
Pulse duration (width), PCLK low
tlow
11
ns
tr, tf
Slew rate, PCLK
v/t
1
4
V/ns
tw
Pulse duration (width), GRST
trst
1
ms
tsu
Setup time, PCLK active at end of PRST
trst-clk
100
ms