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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 264/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SNA7412ZHK |
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PC Card Controller Programming Model
76
September 2005
SCPS110
4
PC Card Controller Programming Model
This chapter describes the PCIxx12 PCI configuration registers that make up the 256-byte PCI configuration
header for each PCIxx12 function. There are some bits which affect more than function 0, but which, in order
to work properly, must be accessed only through function 0. These are called global bits. Registers containing
one or more global bits are denoted by § in Table 42.
Any bit followed by a is not cleared by the assertion of PRST (see CardBus Bridge Power Management,
Section 3.8.10, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared
only by GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes
referred to as PME context bits and are implemented to allow PME context to be preserved during the
transition from D3hot or D3cold to D0.
If a bit is followed by a , then this bit is cleared only by GRST in all cases (not conditional on PME being
enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC
programming during warm resets.
A bit description table, typically included when the register contains bits of more than one type or purpose,
indicates bit field names, a detailed field description, and field access tags which appear in the type column.
Table 41 describes the field access tags.
Table 41. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
MEANING
R
Read
Field can be read by software.
W
Write
Field can be written by software to any value.
S
Set
Field can be set by a write of 1b. Writes of 0b have no effect.
C
Clear
Field can be cleared by a write of 1b. Writes of 0b have no effect.
U
Update
Field can be autonomously updated by the PCIxx12 controller.
4.1
PCI Configuration Register Map (Function 0)
The PCIxx12 controller is a multifunction PCI device, and the PC Card controller is integrated as PCI function
0. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is
PC99/PC2001 compliant as well. Table 42 illustrates the PCI configuration register map, which includes both
the predefined portion of the configuration space and the user-definable registers.
Table 42. Function 0 PCI Configuration Register Map
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Latency timer
Cache line size
0Ch
CardBus socket registers/ExCA base address register
10h
Secondary status
Reserved
Capability pointer
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
PCI bus number
18h
CardBus memory base register 0
1Ch
CardBus memory limit register 0
20h
CardBus memory base register 1
24h
CardBus memory limit register 1
28h
One or more bits in this register are cleared only by the assertion of GRST.
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