參數(shù)資料
型號： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁數(shù)： 71/81頁
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
73
6.3.17 Port Device Status Register
Address Offset: F80H (PM Port 0)/ F88H (PM Port 1) / F90H (PM Port 2) / F98H (PM Port 3) / FA0H (PM Port 4) / FA8H (PM Port
5) / FB0H (PM Port 6) / FB8H (PM Port 7) / FC0H (PM Port 8) / FC8H (PM Port 9) / FD0H (PM Port 10) / FD8H (PM Port 11) /
FE0H (PM Port 12) / FE8H (PM Port 13) / FF0H (PM Port 14) / FF8H (PM Port 15)
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
reserved
serv
ice
_
pending
legac
y
_queu
e
nat
ive_qu
e
ue
devic
e_bus
y
exec_active_slot
pio_end_status
These 16 registers contain information useful for diagnosing behavior of the execution unit. These 16 registers contain Port
Multiplier device specific information. Address Offset bits 6 to 3 are the Port Multiplier Port number for the device to which the
status bits apply. There is one register for each of 16 possible port multiplier ports. These registers are part of the LRAM.
Bit [31:17]: Reserved
Bit [16]: service_pending (R/W). Indicates that a service request has been received from this device and a
SERVICE command has not yet been acknowledged.
Bit [15]: legacy_queue (R/W). Indicates that one or more legacy queued commands are outstanding to this
device.
Bit [14]: native_queue (R/W). Indicates that one or more native queued commands are outstanding to this
device.
Bit [13]: device_busy (R/W). Virtual BSY bit indicating that a command has been issued to the device without
receipt of a final register FIS or that a data transfer is in progress.
Bit [12:08]: exec_active_slot (R/W). Contains the slot number of the last command active on this device.
Bit [07:00]: pio_end_status (R/W). Contains the PIO ending status of the last PIO setup command received
from this device.
6.3.18 Port Device QActive Register
Address Offset: F84H (PM Port 0)/ F8CH (PM Port 1) / F94H (PM Port 2) / F9CH (PM Port 3) / FA4H (PM Port 4) / FACH (PM
Port 5) / FB4H (PM Port 6) / FBCH (PM Port 7) / FC4H (PM Port 8) / FCCH (PM Port 9) / FD4H (PM Port 10) / FDCH (PM Port
11) / FE4H (PM Port 12) / FECH (PM Port 13) / FF4H (PM Port 14) / FFCH (PM Port 15)
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
QActive[31:0]
These 16 registers contain Port Multiplier device specific status indicating outstanding queued commands in the device. For
each bit set to one, a queued command, legacy or native, is outstanding associated with the slot number corresponding to the
bit position. There is one register for each of 16 possible port multiplier ports. Address Offset bits 6 to 3 are the Port Multiplier
Port number for the device to which the status bits apply.
Bit [31:00]: Each bit corresponds to a slot number that contains an active outstanding legacy or native queued
command.
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