參數(shù)資料
型號： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁數(shù)： 40/81頁
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
45
6.1.3
PCI Class Code – Revision ID
Access Type: Read/Write
Reset Value: 0x0180_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Class Code
Revision ID
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:08]: PCI Class Code (R) – PCI Class Code. This value in this bit field is one of the following:
the default value of 018000h for Mass Storage Class.
system programmed value; if bit 0 of the Configuration register (48H) is set the PCI Class Code is system
programmable.
Bit [07:00]: Revision ID (R) – Chip Revision ID. This bit field is hardwired to indicate the revision level of the chip
design; revision 01H is defined by this specification.
6.1.4
BIST – Header Type – Latency Timer – Cache Line Size
Address Offset: 0CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST
Header Type
Latency Timer
Cache Line Size
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]: BIST (R). This bit field is hardwired to 00H.
Bit [23:16]: Header Type (R). This bit field is hardwired to 00H.
Bit [15:08]: Latency Timer (R). This field is hardwired to 00H.
Bit [07:00]: Cache Line Size (R/W). This bit field is Read/Write for legacy purposes. The field is not used by the
SiI3531A.
6.1.5
Base Address Register 0
Address Offset: 10H
Access Type: Read/Write
Reset Value: 0x0000_0000_0000_0004
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Base Address Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 0
0000100
This register defines the addressing of the Global Registers within the SiI3531A. The register bits are defined below.
Bit [63:07]: Base Address Register 0 (R/W). This register defines the base address for the 128-byte Memory
Space containing the Global Registers.
Bit [06:00]: (R). This bit field is hardwired to 0000100B to indicate a 64-bit base address.
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