參數(shù)資料
型號(hào)： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁數(shù)： 61/81頁
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
64
be sent. This bit should be set to the same value as derived from word 0 of the identify packet command
returned data.
Bit [4]: LED Disable (R/W). This bit disables the operation of the LED Port Activity indicator.
Bit [3]: Interrupt No Clear on Read (W1S). When this bit is set to one, a command completion interrupt may be
cleared only by writing a one to the Command Completion bit in the Port Interrupt Status register. When this bit
is zero, reading the Port Slot Status register may also be used to clear the Command Completion interrupt.
Bit [2]: Port Initialize (W1S). Setting this bit to one causes all commands to be flushed from the port and all
command execution parameters to be set to an initialized state. Setting this bit to one causes the port ready bit
in the port status register to be cleared to zero. When the initialization procedure is complete, the port ready bit
will be set to one. This bit is self-clearing and will be cleared upon execution by the port.
Bit [1]: Device Reset (W1S). Setting this bit to one causes all commands to be flushed from the port and all
command execution parameters to be set to an initialized state. Setting this bit to one causes the port ready bit
in the port status register to be cleared to zero. The port will generate the COMRESET primitive on the serial
ATA bus. When the out of band sequence and initialization procedure is complete, the port ready bit will be set
to one. This bit is self-clearing and will be cleared upon execution by the port.
Bit [0]: Port Reset (W1S). Setting this bit to one causes the port to be held in a reset state. No commands will
be executed while in this state. All port registers and functions are reset to their initial state, except as noted
below. All commands are flushed from the port and all command execution parameters are set to an initialized
state. Setting this bit to one causes the port ready bit in the port status register to be cleared to zero. Upon
setting this bit to zero from an asserted state, the port will generate the COMRESET primitive on the serial ATA
bus. When the out of band sequence and initialization procedure is complete, the port ready bit will be set to
one. This bit is set to one by the Global reset, which is set by a PCI reset, and remains set until cleared by the
host (by writing a one to bit 0 of the Port Control Clear register).
The register bits that are not initialized by the Port Reset are:
OOB Bypass (bit 25) in Port Control (this register)
Port PHY Configuration register (all bits)
6.3.4
Port Status
Address Offset: 1000H
Access Type: Read
Reset Value: 0x001F_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Port
R
e
ady
Reserved
OOB
Bypas
s
Reserved
Active Slot
LED
On
A
u
to
Int
e
rlock
A
c
cep
t
PM
Enable
Int
e
rlock
A
ccept
Int
e
rlock
R
e
je
ct
32-
b
it
A
c
ti
vat
ion
Scrambl
e
Dis
a
ble
CONT
Dis
a
b
le
Transmit
BIST
R
esume
Pac
k
et
Length
LE
D
Dis
a
bl
e
Inte
rrupt
NCoR
Port
Init
ializ
e
De
v
ice
Re
se
t
Port
R
e
set
This register is used to determine the status of various port functions.
Bit [31]: Port Ready (R). This bit reports the Port Ready status. The transition from 0 to 1 of this bit generates
the Port Ready Interrupt Status (bit 18/2 of the Port Interrupt Status register).
Bit [30:26,24:21]: Reserved (R). These bits are reserved.
Bit [20:16]: Active Slot (R). This bit field contains the slot number of the command currently being executed.
When a command error occurs, this bit field indicates the slot containing the command in error.
Bit [25,15:0]: These bits reflect the current state of the corresponding bits in the Port Control register. Refer to
the Port Control Set register for a complete description.
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