參數(shù)資料
型號： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁數(shù)： 49/81頁
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
53
6.1.24 Port Register Offset
Address Offset: F8H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Dword Offset
00
This register provides indirect addressing of a Port Register otherwise accessible directly via Base Address Register 1. The
Dword address offset for an indirect access is in bits 12 to 2; bits 31 to 13, 1, and 0 are reserved and should always be 0.
Note that this is physically the same register as that addressed by Base Address Register 2, Offset 08H.
6.1.25 Port Register Data
Address Offset: FCH
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the Port Register Offset register.
6.1.26 Advanced Error Reporting Capability
Address Offset: 100H
Access Type: Read Only
Reset Value: 0x0001_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Next Capability Pointer
Version
Extended Capability ID
Bit [31:20]: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired to 000H (this is
the last capability).
Bit [19:16]:
Version (R) – This bit field is hardwired to 01H to indicate compliance with the PCI Express
Specification revision 1.0a.
Bit [15:00]: Extended Capability ID (R) – PCI Capability ID. This bit field is hardwired to 0001H to indicate that
this is an Advanced Error Reporting Capability.
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