參數(shù)資料
型號(hào)： SII3531ACNU
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁(yè)數(shù)： 53/81頁(yè)
文件大小： 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
57
6.2.1
Port Slot Status Register
Address Offset: 00H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Attention
Slot Status
This register provides the Status for the 31 Command Slots for the port. This register also appears in Port register space.
Reading this register will clear the Command Completion Status for the port if the Interrupt No Clear on Read bit (bit 3) of the
Port Control register is 0. The register bits are defined below.
Bit [31]: Attention (R) – This bit indicates that something occurred that requires the attention of the host. Other port
registers must be examined to determine the origin of the error. This bit is the logical OR of the masked interrupt
conditions, except for Command Completion, reported in the Port Interrupt Status register.
Bit [30:0]: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit for a slot is set when the Slot number is written to the Command Execution FIFO (direct command transfer
method) or when a Command Activation register is written (indirect command transfer method).
6.2.2
Global Control
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x8100_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Global
Re
set
MS
IACK
Reserved
3Gb/s
C
a
pable
Arbiter Control
Reserved
Port
Int
Enable
This register controls various functions of the chip.
Bit [31]: Global Reset (R/W). This bit, when set to one, asserts a port reset to all ports. This bit must be cleared to
zero to allow normal operation. Once set by this bit, all port resets will remain set to one until explicitly cleared to
zero through the individual port control clear registers. Refer to the port control set register description for more
information.
Bit [30]: MSI Acknowledge (W). Writing a one to this bit acknowledges a Message Signaled Interrupt and permits
generation of another MSI. This bit is cleared immediately after the acknowledgement is recognized by the control
logic, hence the bit will always be read as a zero. If all interrupt conditions are removed subsequent to an MSI, it is
not necessary to assert this Acknowledge; another MSI will be generated when an interrupt condition occurs.
Bit [29:25,15:1]: Reserved (R). These bits are reserved and will return zeroes when read.
Bit [23:16]: Arbiter Control (R/W). This bit field, when set to 42H, selects an alternate arbitration algorithm.
Bit [24]: 3Gb/s Capable (R). This bit is always one to indicate that the device is configured and tested for 3Gb/s (S-
ATA generation 2) operation.
Bit [0]: Port Interrupt Enable (R/W). This bit, when set to one, allows assertion of an interrupt when the port asserts
an interrupt. When set to zero, the port interrupts are masked.
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