參數(shù)資料
型號(hào)： SII3531ACNU
元件分類(lèi)： 總線(xiàn)控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁(yè)數(shù)： 39/81頁(yè)
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
44
6.1.1
Device ID – Vendor ID
Address Offset: 00H
Access Type: Read /Write
Reset Value: 0x3531_1095
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device ID
Vendor ID
This register defines the Device ID and Vendor ID associated with the SiI3531A. The register bits are defined below.
Bit [31:16]: Device ID (R/W) – Device ID. The value in this bit field is one of the following:
the default value of 0x3531 to identify the device as a Silicon Image SiI3531A.
system programmed value; if bit 0 of the Configuration register (48H) is set, the Device ID is system
programmable.
Bit [15:00]: Vendor ID (R) – Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon Image.
6.1.2
PCI Status – PCI Command
Address Offset: 04H
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x0010_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Det
Par
E
rr
Sig
Sy
s
Err
Rc
v
d
M
Abort
Rcvd
T
Abort
Sig
T
Abort
Re
s
e
rv
e
d
De
tM
P
a
rE
rr
Re
s
e
rv
e
d
Capabilit
ie
s
List
Int
St
at
us
Reserved
Int
D
isable
Re
s
e
rv
e
d
SER
R
Enabl
e
Re
s
e
rv
e
d
Par
Er
ror
Resp
Re
s
e
rv
e
d
B
u
s
M
ast
er
Memory
Spa
ce
IO
Spa
c
e
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit 31: Det Par Err (R/W1C) – Detected Parity Error.
Bit 30: Sig Sys Err (R/W1C) – Signaled System Error.
Bit 29: Rcvd M Abort (R/W1C) – Received Master Abort.
Bit 28: Rcvd T Abort (R/W1C) – Received Target Abort.
Bit 27: Sig T Abort (R/W1C) – Signaled Target Abort.
Bit 24: Det M Par Err (R/W1C) – Detected Master Data Parity Error.
Bit 20: Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI3531A
implements Capabilities registers for Power Management, PCI-X, and Message Signaled Interrupt.
Bit [19]: Interrupt Status (R).
Bit [26:25,23:21,18:11,9,7,5:3]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [10]: Interrupt Disable (R/W).
Bit 08: SERR Enable (R/W) – SERR Enable.
Bit 06: Par Error Resp (R/W) – Parity Error Response Enable.
Bit 02: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI3531A to act as PCI bus master, i.e.,
issue Memory Requests.
Bit 01: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3531A to respond to memory
space accesses.
Bit 00:
I/O Space (R/W) – I/O Space Enable.
This bit set enables the SiI3531A to respond to I/O space
accesses.
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