參數(shù)資料
型號(hào)： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁(yè)數(shù)： 68/81頁(yè)
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
70
6.3.12 Port PCI Express Request FIFO Threshold
Address Offset: 102CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
PCI Exp Write Request Threshold
Reserved
PCI Exp Read Request Threshold
Reserved
This register contains threshold levels at which the PCI Express master state machine will request the PCI Express bus
relative to the amount of data or free space in the data FIFO. The data FIFO capacity is 2Kbyte (256 Qwords). When
writing to host memory (reading data from a device), the PCI Express Write Request Threshold is compared to the
amount of data in the data FIFO. When the FIFO contents exceed the threshold value, a request is issued to write the
data to host memory, emptying the contents of the data FIFO. When reading host memory (writing data to a device) the
PCI Express Read Request Threshold is compared to the amount of free space in the data FIFO. When the free space
exceeds the threshold value, a request is issued to read data from host memory to fill the FIFO.
Bit [31:27]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [26:19]: PCI Exp Write Request Threshold (R/W). This field defines the number of Qwords that must be in
the data FIFO before issuing a PCI Express request. A value of zero will cause a request if the FIFO contains
any amount of data.
Bit [18:16]: Reserved (R). This bit field is reserved and returns zeros on a read. This field is defined so that the
host may write a byte count value into the threshold register.
Bit [15:11]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [10:3]: PCI Exp Read Request Threshold (R/W). This field defines the number of Qwords that must be
available in the data FIFO before issuing a PCI Express request. A value of zero will cause a request if the FIFO
contains any free space and the DMA is active.
Bit [2:0]: Reserved (R). This bit field is reserved and returns zeros on a read. This field is defined so that the
host may write a byte count value into the threshold register.
6.3.13 Port 8B/10B Decode Error Counter
Address Offset: 1040H
Access Type: Read/Write/Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
8B/10B Decode Error Threshold
8B/10B Decode Error Counter
This register counts the number of 8B/10B Decode Errors that have occurred since last cleared.
Bit [31:16]: 8B/10B Decode Error Threshold (R/W). This bit field defines the count at which an interrupt will be
asserted. When the count in bits 15:0 is equal to this value, an 8B/10B interrupt will be latched. A threshold
value of zero disables interrupt assertion and masks the corresponding interrupt status bit in the Port Interrupt
Status register.
Bit [15:0]: 8B/10B Decode Error Count (R/WC). This bit field represents the count of 8B/10B errors that have
occurred since this register was last written. Any write to this register field will clear both the counter and the
interrupt condition. Clearing the interrupt status bit will also clear the counter. The count will not overflow. Once
this register reaches its maximum count, it will retain that count until cleared to zero by a write operation.
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