參數(shù)資料
型號(hào)： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁(yè)數(shù)： 62/81頁(yè)
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
65
6.3.5
Port Control Clear
Address Offset: 1004H
Access Type: Write One To Clear
Reset Value: N/A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
OOB
Bypas
s
Reserved
LED
On
Auto
I
n
te
rl
oc
k
Acc
e
p
t
PM
Enable
Re
s
e
rv
e
d
3
2
-bi
tAc
ti
v
a
ti
on
Scrambl
e
Dis
a
ble
CONT
Dis
a
b
le
Transmit
BIST
R
esume
Pac
ket
Length
LE
D
Dis
a
b
le
Inte
rrupt
NCoR
Re
s
e
rv
e
d
Port
R
eset
This register is used to direct various port operations. A one written to a bit position clears that bit in the control register.
Bit [31:26,24:16,12:11,2:1]: Reserved (R). These bits are reserved.
Bit [25,15:13,10:3,0]: (W1C) Writing a one to these bits clears the associated bit position of the Port Control
register. Refer to the Port Control Set register for bit descriptions.
6.3.6
Port Interrupt Status
Address Offset: 1008H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
S
DB
Notify
Hshk
Error
Thr
esh
CRC
E
rror
Thre
s
h
8b/10
Error
Thr
esh
DevEx
c
hg
Unre
c
F
IS
C
o
mwake
PhyRdyChg
PM
Change
Port
R
eady
Command
Error
Cmd
Completion
Reserved
S
DB
Notify
Hshk
Error
Thr
esh
CRC
E
rror
Thre
s
h
8b/10
Error
Thr
esh
DevEx
c
hg
Unre
c
F
IS
C
o
mwake
PhyRdyChg
PM
Change
Port
R
eady
Command
Error
Cmd
Completion
This register is used to report the interrupt status. The status bits in the upper half of the register report the described
condition. The status bits in the lower half of the register are masked by the corresponding interrupt enable bits or by the
setting in the corresponding threshold registers. Writing a 1 to either interrupt status bit clears it.
Bit [31:28,15:12]: Reserved (R). These bits are reserved.
Bit [27/11]: SDB Notify (W1C). This bit indicates that a Set Device Bits FIS was received with the N-bit (bit 15
of first dword) set to one.
Bit [26/10]: Handshake Error Threshold (W1C). This bit indicates that the Handshake error count is equal to or
greater than the Handshake error threshold. Bit 10 is masked if the Handshake Error Threshold register contains
a zero threshold setting. When a 1 is written to this bit, both the status bit and the Handshake Error Counter are
cleared.
Bit [25/9]: CRC Error Threshold (W1C). This bit indicates that the CRC error count is equal to or greater than
the CRC error threshold. Bit 9 is masked if the CRC Error Threshold register contains a zero threshold setting.
When a 1 is written to this bit, both the status bit and the CRC Error Counter are cleared.
Bit [24/8]: 8b/10b Decode Error Threshold (W1C). This bit indicates that the 8b/10b Decode error count is
equal to or greater than the 8b/10b Decode error threshold.
Bit 8 is masked if the 8b/10b Decode Error
Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the
8b/10b Decode Error Counter are cleared.
Bit [23/7]: DevExchg (Device Exchanged) (W1C) – This bit is the X bit in the DIAG field of the SError register. It
may be cleared by writing a corresponding one bit to either register.
Bit [22/6]: UnrecFIS (Unrecognized FIS Type) (W1C) – This bit is the F bit in the DIAG field of the SError
register. It may be cleared by writing a corresponding one bit to either register.
Bit [21/5]: ComWake (W1C) – This bit is the W bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [20/4]: PhyRdyChg (W1C) – This bit is the N bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [19/3]: PM Change (W1C). This bit indicates that a change has occurred in the power management state.
相關(guān)PDF資料
PDF描述
SIO10N268-NU MULTIFUNCTION PERIPHERAL, PQFP128
SIS300 GRAPHICS PROCESSOR, PBGA365
SK12430PJT 800 MHz, OTHER CLOCK GENERATOR, PQCC28
SK12439PJ 800 MHz, OTHER CLOCK GENERATOR, PQCC28
SK12439PJT 800 MHz, OTHER CLOCK GENERATOR, PQCC28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3611 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge
SII3611CT80-1.5 制造商:SILICON IMAGE 功能描述:3611CT80-1.5
SII3723 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:Third Generation SATA Port Multiplier Storage Processor
SiI3723CNU 制造商:Silicon Image Inc 功能描述:
SII3726 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATA Port Multiplier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*