參數(shù)資料
型號(hào)： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁(yè)數(shù)： 65/81頁(yè)
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
68
Table 6-8 Command Error Codes
Error Name
Code
Description
DEVICEERROR
1
The ERR bit was set in a "register - device to host" FIS received from the
device. The task file registers are written back to PRB slot for host scrutiny.
SDBERROR
2
The ERR bit was set in a "set device bits" FIS received from the device.
DATAFISERROR
3
The SiI3531A detected an error during command execution that was not
reported by the device upon command completion.
SENDFISERROR
4
The SiI3531A was unable to send the Initial command FIS for a command.
This can occur if a low-level link error occurs during command transmission.
INCONSISTENTSTATE
5
The SiI3531A detected an inconsistency in protocol. Any departure from
standard Serial ATA protocol that causes indecision in the internal sequencers
will cause this error.
DIRECTIONERROR
6
A Data FIS was received when a write data protocol was specified or a DMA
Activate FIS was received when a read data protocol was specified.
UNDERRUNERROR
7
While transferring data from the SiI3531A to a device, the end of the Scatter
Gather list was encountered before the entire transfer was completed. The
device is requesting additional data but there is no Scatter Gather Entry to
define the source of data.
OVERRUNERROR
8
While transferring data from a device to the SiI3531A, the end of the Scatter
Gather list was encountered before the entire transfer was completed. Data
was received from the device but there is no Scatter Gather Entry to define
where the data should be deposited.
PACKETPROTOCOLERROR
11
During the first PIO setup of Packet command, the data direction bit was
invalid, indicating a transfer from device to host.
PLDSGTERRORBOUNDARY
16
A requested Scatter Gather Table not aligned on a quadword boundary. All
addresses defining Scatter Gather Tables must be quadword aligned. Bits[2:0]
must be zeroes.
PLDSGTERRORTARGETABORT
17
A PCI Target Abort occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
PLDSGTERRORMASTERABORT
18
A PCI Master Abort occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
PLDSGTERRORPCIPERR
19
A PCI Parity Error occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
PLDCMDERRORBOUNDARY
24
The address of a PRB written to a command activation register was not aligned
on a quadword boundary. All PRB addresses must be quadword aligned.
Bits[2:0] must be zeroes.
PLDCMDERRORTARGETABORT
25
A PCI Target Abort occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
PLDCMDERRORMASTERABORT
26
A PCI Master Abort occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
PLDCMDERRORPCIPERR
27
A PCI Parity Error occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
PSDERRORTARGETABORT
33
A PCI Target Abort occurred while data transfer was underway between the
SiI3531A and host memory.
PSDERRORMASTERABORT
34
A PCI Master Abort occurred while data transfer was underway between the
SiI3531A and host memory.
PSDERRORPCIPERR
35
A PCI Parity Error occurred while data transfer was underway between the
SiI3531A and host memory.
SENDSERVICEERROR
36
A FIS was received while attempting to transmit a Service FIS. Following the
receipt of a Set Device Bits FIS containing a service request, the device sent
another FIS before allowing the host to send a Service FIS.
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