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參數(shù)資料
| 型號(hào)： | SII3531ACNU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, QCC48 |
| 封裝： | 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48 |
| 文件頁數(shù)： | 17/81頁 |
| 文件大小： | 532K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
24
5.3.3
The Scatter/Gather Table (SGT)
The SGT is simply a contiguous collection of four SGEs. The PRB contains two SGEs. When more than two SGEs are
required to fully define the entire data transfer of a command, the SiI3531A fetches additional SGEs in groups of four at a time,
or one SGT. The SGT occupies the upper 64 bytes of a command slot in SiI3531A RAM. When needed, only one SGT
resides in RAM at a time. The SiI3531A fetches each required SGT, overwriting the previous SGT in RAM. Since the first two
SGEs reside in the PRB RAM area, they are always available in case the SiI3531A needs to rescan the scatter/gather list for
out of order data delivery.
SGTs must reside on a quadword (64-bit) naturally aligned boundary in host memory. In other words, bits[2:0] of the physical
address of the SGT in host memory must be zero.
31
0
SGE0 Data Address Low
0x00
SGE0 Data Address High
0x04
SGE0 Data Count
0x08
SGE0 TRM
SGE0 LNK
SGE0 DRD
SGE0 XCF
Reserved[27:0]
0x0C
SGE1 Data Address Low
0x10
SGE1 Data Address High
0x14
SGE1 Data Count
0x18
SGE1 TRM
SGE1 LNK
SGE1 DRD
SGE1 XCF
Reserved[27:0]
0x1C
SGE2 Data Address Low
0x20
SGE2 Data Address High
0x24
SGE2 Data Count
0x28
SGE2 TRM
SGE2 LNK
SGE2 DRD
SGE2 XCF
Reserved[27:0]
0x2C
SGE3 Data Address Low
0x30
SGE3 Data Address High
0x34
SGE3 Data Count
0x38
SGE3 TRM
SGE3 LNK
SGE3 DRD
SGE3 XCF
Reserved[27:0]
0x3C
Table 5-2 Scatter/Gather Table (SGT)
5.3.4
The Port Request Block (PRB)
The host builds a PRB to define a command to be executed by the SiI3531A. The PRB occupies the first 64 bytes of a
command slot in SiI3531A RAM. Once a command is issued, the PRB is overwritten in SiI3531A RAM as necessary to keep
track of command context and execution status. The host should not depend on being able to read the contents of the PRB in
slot RAM after command issuance. Upon command execution completion, the PRB area of the command slot may contain
status information that can be read by the host, dependent upon the command type. The PRB structure can take several
forms, dependent upon the command type that it defines.
The PRB contains the following major elements:
A Control Field to indicate the type of PRB and any features to execute.
A Protocol Override field used to optionally alter the normal SATA protocol flow.
A FIS area that contains the initial FIS to be transmitted to the device upon PRB execution.
Up to two Scatter/Gather entries (SGEs) to define areas of host memory that will be used for any data transfer
associated with the PRB. For PACKET commands, the first SGE contains the 12 or 16-byte ATAPI command to
be transmitted to the device.
Regardless of whether the command is to be issued with the direct or indirect method, the host driver should build the PRB as
a structure in host memory. If the command is to be issued using the direct issuance method, the PRB can be copied from
host RAM to the appropriate slot in SiI3531A RAM. If the command is to be issued using the indirect method, the host driver
should write the physical address of the PRB to the command activation register associated with the desired command slot.
The PRB must reside on a quadword (64-bit) naturally aligned boundary in host memory. In other words, bits[2:0] of the
physical address of the PRB in host memory must be zero.
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