參數(shù)資料
型號(hào)： SII3531ACNU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, QCC48
封裝： 7 X 7 MM, 0.40 MM PITCH, LEAD FREE, QFN-48
文件頁數(shù)： 42/81頁
文件大?。?/td> 532K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
47
6.1.9
Capabilities Pointer
Address Offset: 34H
Access Type: Read
Reset Value: 0x0000_0054
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Capabilities Pointer
This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:00]: Capabilities Pointer (R) – Capabilities Pointer. This bit field contains 54H, the address for the 1
st
Capabilities register set, the PCI Power Management Capability.
6.1.10 Max Latency – Min Grant – Interrupt Pin – Interrupt Line
Address Offset: 3CH
Access Type: Read/Write
Reset Value: 0x0000_0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
This register defines various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]: Max Latency (R) – Maximum Latency. This bit field is hardwired to 00H.
Bit [23:16]: Min Grant (R) – Minimum Grant. This bit field is hardwired to 00H.
Bit [15:08]: Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01H to indicate that the SiI3531A
uses the INTA interrupt.
The INTB, INTC, and INTD interrupts may be used by enabling them in the Port
Interrupt Enable registers; this use is outside the PCI specification.
Bit [07:00]: Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt line
routing information. The SiI3531A does not use this information.
6.1.11 Header Write Enable
Address Offset: 48H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Ind
A
cc
En
a
Hdr
Wr
E
n
a
Bit [31:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01]: Ind Acc Ena (R) – Indirect Access Enable. This bit enables the Indirect Access registers at offset F0H-
FFH.
Bit [00]: Hdr Wr Ena (R) – Header Write Enable. This bit enables writing to registers defined as read-only by
the PCI specification. This bit is required to meet PCI compliance testing that expects certain registers to be
read-only. This bit is set to enable write access to the following registers in the PCI Configuration Header:
Device ID (03-02H), PCI Class Code (09-0BH), Subsystem Vendor ID (2D-2CH), and Subsystem ID (2F-2EH).
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