參數(shù)資料
型號(hào)： SCANSTA101
廠商： National Semiconductor Corporation
英文描述： RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述： 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù)： 5/31頁(yè)
文件大?。?/td> 403K
代理商： SCANSTA101
AC Electrical Characteristics/Operating Requirements
supply voltage and temperature ranges unless otherwise specified. C
L
= 50 pF, R
L
= 500
unless otherwise specified.
Over recommended operating
Symbol
Parameter
Conditions
# of SCK
(Notes 3, 4)
Min
Max
Units
PARALLEL PROCESSOR INTERFACE (PPI)
t
S1
Set Up Time
CE, R/W, Addr, Data to STB
t
H1
Hold Time
CE, R/W, Addr, Data to STB
t
D1
Propagation Delay
STB low to DTACK low, Register Write
t
D1
Propagation Delay
STB low to DTACK low, Register Read
t
D1
Propagation Delay
STB low to DTACK low, Memory Write: 16-bit first
access
t
D1
Propagation Delay
STB low to DTACK low, Memory Write: 16-bit second
access
t
D1
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit first
access
t
D1
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit
second access
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Register Write
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Register Read
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Memory Write:
16-bit first access
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Memory Write:
16-bit second access
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Memory Read:
16-bit first access
t
D2
Propagation Delay
STB high to DTACK TRISTATE, Memory Read:
16-bit second access
t
D3
Propagation Delay
Output data valid to DTACK low, all read cycles
t
pHL1
Propagation Delay
STB low to INT low, register write (clears Interrupt)
t
W
Clock Pulse Width, SCK, H or L
f
MAX
Clock Frequency, SCK
t
RELEASE
Release Time, RST to STB
Figures 11, 12
0
ns
Figures 11, 12
0
ns
Figure 11
2 or 3
11.5
ns
Figure 12
4 or 5
11.5
ns
Figure 11
3 or 4
11.5
ns
Figure 11
7 or 8
11.5
ns
Figure 12
9 or 10
11.5
ns
Figure 12
3 or 4
11.5
ns
Figure 11
1 or 2
10.0
ns
Figure 12
1 or 2
10.0
ns
Figure 11
1 or 2
10.0
ns
Figure 11
1 or 2
10.0
ns
Figure 12
1 or 2
10.0
ns
Figure 12
1 or 2
10.0
ns
Figure 12
1
ns
Figure 11
5 or 6
10.5
ns
3.0
ns
MHz
ns
66
2
Note 3:
Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4:
An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + t
D
.
For example, for t
(STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, t
D
, is 11.5ns. For a SCK with a 100ns period, the absolute
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
S
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參數(shù)描述
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SCANSTA101SM/NOPB 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA101SM/NOPB 制造商:Texas Instruments 功能描述:Test Master IC
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