參數(shù)資料
型號(hào): SCANSTA101
廠商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù): 21/31頁(yè)
文件大?。?/td> 403K
代理商: SCANSTA101
Hardware Interface Details
(Continued)
TABLE 15. Parallel Processor Interface Signal Descriptions
(Continued)
Pin Type
Driver Type
Freq.
MHz
I
LVTTL
N/A
Signal Name
No. of
Bits
1
Description
CE
Chip Enable, when low, enables the PPI for transfers.
DATA(31:0) and DTACK are tristated when CE is high.
Read/Write defines a PPI cycle. Read when high, write when
low.
Strobe is used for timing all PPI transfers. DATA(31:0) are
tristated when STB is high. Data valid setup is with respect
to the falling edge of STB and data valid hold is with respect
to rising edge of STB.
Data Acknowledge (open drain - sustained tristate). DTACK
is used to synchronize asynchronous transfers between the
host and the STA101. During write cycles, DTACK goes low
when data has been registered and then goes to high
impedance when the cycle has been completed. During read
cycles DTACK goes low when data bus is driven with the
valid data and then goes to high impedance when the cycle
has been completed.
Interrupt is used to trigger a host interrupt for any of the
defined interrupt events. Signal is active high.
R/W
1
I
LVTTL
N/A
STB
1
I
LVTTL
N/A
DTACK
1
O
O/D
N/A
INT
1
O
LVTTL
N/A
10121537
FIGURE 11. PPI Write Cycle Timing Diagram
S
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