參數(shù)資料
型號: SCANSTA101
廠商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁數(shù): 14/31頁
文件大小: 403K
代理商: SCANSTA101
Serial Scan Interface
(Continued)
The TDI_SM shifter unit consists of two 32-bit shift registers
as shown in
Figure 4
. The shift register on top will be used as
an LFSR register. However, before using the TDI_SM LFSR
register, the LFSR Exponent and LFSR Seed registers must
be written with valid data. The LFSR Exponent register must
be written with a 3-bit binary encoded value such that the
corresponding polynomial out of the five available polynomi-
als will be selected. The value written to the LFSR Seed
registers will be used to initialize the TDI_SM LFSR register
to a predetermined state. Once the test vector has com-
pletely scanned in, the final contents of the LFSR register will
be transferred to the LFSR Result registers. The 32-bit shift
register at the bottom will be used to shift in TDI_SM directly
in normal mode or to shift in TMS_SM or TDO_SM in the
loop-back mode. After shifting in every thirty two bits, the
contents of this register will be transferred to the correspond-
ing TDI memory location before the next shift operation.
SHIFTER IMPLEMENTATION
Shift register implementation is illustrated in
Figure 5
. Shift
out enable for the TMS_SM and TDO_SM shifters is gener-
ated by comparing the clock pulse counter output to the
clock divider - 1. Shift in enable for the TDI_SM shifter is
generated by comparing the clock pulse counter to program-
mable divisor/2 - 1. These enables are gated by the control
signals from SSIC so that data are shifted out (TMS_SM/
TDO_SM) or shifted in (TDI_SM) only when necessary.
10121523
FIGURE 4. TDI_SM Shifter
S
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