- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376340 > SCANSTA101 (National Semiconductor Corporation) RES 30K OHM 1/16W 0.1% 0402 SMD PDF資料下載
參數(shù)資料
| 型號： | SCANSTA101 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | RES 30K OHM 1/16W 0.1% 0402 SMD |
| 中文描述： | 低壓主STA的IEEE 1149.1標準 |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 403K |
| 代理商： | SCANSTA101 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
Serial Scan Interface
(Continued)
9.
If the macro type is Shift or Shift with Capture then,
A. If the macro type is Shift with Capture, enable TDI
capture.
B. If the Sync Bit Support Enable bit is set, fetch sync bit
count, set the count length, set TMS_SM to the loop
bit and drive the TDO_SM high until sync bit count is
zero.
C. If the ScanBridge Support Initiate/Release bit is set,
drive the TDO_SM with pre- PAD bit (high) and while
TMS_SM remains set to the loop bit. Repeat for each
level of hierarchy.
D. If the Use Data/Instruction Header is enabled, fetch
the header length and data, set the count length, and
drive the TDO_SM with header data until the header
length is zero and while TMS_SM remains set to the
loop bit.
E. If the Compare or Mask/Compare is set, enable the
comparator.
F. Set the vector count length, and drive the TDO_SM
with vector data until the count length is one and
while TMS_SM remains set to the loop bit. In the LotF
mode if the count length is not zero and the TDO
buffer is empty, then gate TCK_SM until more data
are available in the TDO buffer. When TCK_SM is
disabled TMS_SM and TDO_SM will be driven with
their previous values.
G. If the Use Data/Instruction Trailer is enabled, fetch
the trailer length and data, set the count length, and
drive TDO_SM with trailer data until the trailer length
is one and while TMS_SM remains set to the loop
bit.
H. If the ScanBridge Support Initiate/Release bit is set:
a. If the TAP tracker is in the Shift-IR state and the
number of levels of hierarchy is greater than one,
set the count length to eight, and drive TDO_SM
with post-PAD bits (all high) until the count length
is zero for each level of hierarchy and while
TMS_SM remains set to the loop bit.
b. If the TAP tracker is in the Shift-DR state and the
number of levels of hierarchy is greater than one,
drive TDO_SM with a post-PAD bit (high) for each
level of hierarchy and while TMS_SM remains set
to the loop bit.
c. For the final level of hierarchy or if there is only
one level of hierarchy, and if the TAP tracker is in
the Shift-IR state, set the count length to eight,
and drive TDO_SM with post-PAD bits (all high)
until the count length is one and while TMS_SM
remains set to the loop bit.
I. If the Sync Bit Support Enable is set, fetch sync bit
count, set the count length, and drive the TDO_SM
high until sync bit count is one and while TMS_SM
remains set to the loop bit.
J. Set TMS_SM to the bit 8 of the TMS_SM Macro
Structure sequence and drive TDO_SM with the final
vector bit or trailer bit or post-PAD bit or sync bit.After
shifting out the final vector bit, disable the comparator
and register the comparison results.
10. If the Post-shift TCK_SM Count is not zero, then enable
TCK_SM and drive TMS_SM using the last seven bits of
the macro until the Post-shift TCK_SM Count is zero.
11. If the Sequencer is being used,
A. Decrement the sequence repeat count and return to
Step 3c if the Compare or Mask/Compare is enabled
and the results of compare is a fail.
B. Decrement the vector repeat count and return to
Step 3e if the if the Compare or Mask/Compare is
enabled and the results of compare is a pass.
C. Decrement the vector repeat count and return to
Step 3e if the Compare or Mask/ Compare is not
enabled.
12. If the Vector is being used return to the Idle state.
MODE REGISTER WRITE TO VECTOR/SEQUENCER START
Figure 7
shows the timing from the processor write to the
start of vector processing, whereas
Figure 8
shows the
timing from the processor write to the start of sequencer
processing. A processor write to the Start registers is indi-
10121533
FIGURE 7. Timing from Mode Register Write to Vector Start
S
www.national.com
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANSTA111SM | EMITTER IR 850NM 5MM RADIAL |
| SCANSTA111 | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| SCANSTA111MT | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| SCANSTA112 | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA112SM | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 制造商:Texas Instruments 功能描述:Test Master IC |
| SCANSTA101SMX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。