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參數(shù)資料
| 型號(hào)： | SCANSTA101 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | RES 30K OHM 1/16W 0.1% 0402 SMD |
| 中文描述： | 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn) |
| 文件頁數(shù)： | 23/31頁 |
| 文件大小： | 403K |
| 代理商： | SCANSTA101 |
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Hardware Interface Details
(Continued)
TABLE 17. STA101 1149.1 Signal Descriptions
Signal Name
No. of
Bits
1
1
1
1
1
Pin Type
Driver Type
Freq.
MHz
up to 25
up to 25
up to 25
up to 25
N/A
Description
TDO
TDI
TMS
TCK
TRST
O
I,U
I,U
I
I,U,H
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
STA101 Test Data Out
STA101 Test Data In (pullup (U))
STA101 Test Mode Select (pullup (U))
STA101 Test Clock
STA101 Test Reset (pullup (U) & hysteresis (H))
TABLE 18. STA101 Scan Signal Descriptions
Signal Name
No. of
Bits
1
1
Pin Type
Driver Type
Freq.
MHz
TBD
TBD
Description
SCAN_EN
SCAN_IN
I
I
Shared TRIST
Shared
DATA15
Shared
DATA14
STA101 Scan Enable Shared pin with TRIST.
STA101 Scan Data In. Shared pin with DATA15.
SCAN_OUT
1
O
TBD
STA101 Scan Data Out. Shared pin with DATA14.
SAFE MODE
This device implements the following design rules to provide
SEU/SEE protection:
Triple
modular
redundancy
TRST1_SM outputs with the help of a TMR D flip-flop .
After reset all scan interface outputs are driven to SEU
tolerant safe values as shown below:
TMS_SM = 1
TCK_SM = 0
TDO_SM = Z
TRST0_SM = 0
TRST1_SM = 0
The EXTEST and the HIGHZ outputs from the JTAG TAP
controller are gated with TRST to protect the boundary
scan cells from inadvertantly entering the test mode.
for
TRST0_SM
and
CLOCK GENERATION AND DISTRIBUTION
Input Clock (SCK): Up to 66 MHz
Output Clock (TCK_SM): TCK_SM is a divided, registered
version of SCK.
Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of
SCK.
Frequency: up to 25 MHz
RESET STRATEGY
The incoming external hardware reset (RST) will be synchro-
nized to the incoming clock (SCK) and is combined with the
soft reset to generate a synchronized internal reset
(SYS_RST_N). During operation, the chip can be reset by
writing a ’1’ to the Reset bit in the Setup register. All logic
throughout the device will be initialized, all control and status
registers will be in a known default state, all PPI memory
address pointers will default to their respective base ad-
dresses, the SSI memory pointer will default to zero, the Tap
Tracker will be reset to TLR, and the clock division counter
will be initialized to all zero’s after deassertion of the internal
reset. The Reset bit in the Setup register is self clearing. The
TRST bit in the Setup register, when set, resets the SSI logic
and drives the TRST0_SM and TRST1_SM to zero.
Software Interface Details
REGISTER DEFINITIONS
The following sections include descriptions of each addres-
sable register in the ScanMaster memory space. Following
the title of the particular register, the mnemonic for the
register is included in parentheses as well as the physical
address location in hexadecimal notation (value preceded by
$).
KEY
- RO: Read Only; RW: Read/Write.
TABLE 19. Start Register (START) ($00)
Bit(s)
Type
Field
Address
Offset
0
0
0
0
0
0
Reset Value
Reset Source
15:14
13
12:9
8
7:3
2:0
RO
RW
RO
RW
RO
RW
Reserved
Onboard Memory BIST
Reserved
Use Sequencer
Reserved Use Vector x (Note 11)
Use Vector x
00b
0b
0000b
0b
0000h
000b
SYS_RST
SYS_RST
SYS_RST
Note 11:
Reserved Use Vector x for future growth for the number of vectors.
S
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相關(guān)代理商/技術(shù)參數(shù) |
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| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 制造商:Texas Instruments 功能描述:Test Master IC |
| SCANSTA101SMX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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