參數(shù)資料
型號(hào)： SCANSTA101
廠商： National Semiconductor Corporation
英文描述： RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述： 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù)： 17/31頁(yè)
文件大?。?/td> 403K
代理商： SCANSTA101
Serial Scan Interface
(Continued)
1.
If the ScanBridge Support Initiate/Release bit was not
set previously and is currently set in the Setup register,
the SSIC initializes the ScanBridge Controller (SBC) to
perform the following steps to set up all ScanBridges in
the hierarchy.
A. Determine the number of levels of ScanBridge sup-
port to be inserted (from the ScanBridge support
structure)
B. Sequence TMS_SM so that all ScanBridges in the
same level of hierarchy enter the SIR state, and then
shift in the address (from the ScanBridge structure)
to select a ScanBridge in the current level of hierar-
chy. The ScanBridge’s TAP controller is then se-
quenced through the Update-IR state.
C. Sequence TMS_SM so that the selected Scan-
Bridge’s TAP controller enters the SIR state, then
scan in the MODESEL instruction to put its mode
register in the data path.
D. Sequence the selected ScanBridge’s TAP controller
to enter the Shift-DR state and scan in the LSP
contents (from the ScanBridge structure) into its
mode register. The ScanBridge’s TAP controller is
then sequenced through the Update-DR state.
E. Repeat Step 1c, but this time scan in the UNPARK
instruction so that the LSP is inserted into the active
scan chain.
F. Sequence the ScanBridge’s TAP controller to enter
the RTI state (the LSP will not be unparked until its
TAP controller enters RTI).
G. Repeat Steps 1b through 1g to configure the Scan-
Bridges in the remaining hierarchy levels. One set of
pre-PAD and post-PAD bits is added to the patterns
for each hierarchy level between the ScanMaster
and the ScanBridge being configured. The PAD bits
are used to bypass the intermediate levels of hierar-
chy.
H. For the subsequent vectors, if the TAP Tracker en-
ters the
a. SDR state, the STA101 will add one pre-bit for the
PAD register and one post-bit for the bypass reg-
ister for each level of hierarchy.
b. SIR state, the STA101 will add one pre-bit for the
PAD register and eight post-bits for the Scan-
Bridge instruction register for each level of hierar-
chy. The eight post-bits will be all ones because
the ScanBridge will be forced into bypass mode.
I. The PAD bits need to be stripped when loading a
vector into TDI_SM. This will be done by having a
status flag to indicate whether the vector that is being
scanned out has ScanBridge support or not. If the
scanned-out vector has ScanBridge support, then the
PAD bits will be stripped when the TAP Tracker enters
the SDR or SIR states.
If the ScanBridge Support Initiate/Release bit was set
previously and is currently reset in the Setup register,
the SSIC will toggle TCK_SM five times while TMS_SM
is held high. This will return all selected ScanBridges to
the wait-for-address state and park the LSPs in the
Test-Logic-Reset state. When the ScanBridge support is
released the user should make sure that the Use Vector
and Use Sequencer bits in the Start register are not set,
such that, the SSIC will not start processing a vector or
2.
the sequencer immediately after releasing the Scan-
Bridge support. However, once the ScanBridge support
is released the user may start processing a vector or the
sequencer by writing to the Start register.
If the sequencer is enabled (the Use Sequencer bit in
the Start register is one),
A. Clear the Results of Compare bit and set the Using
Sequencer bit in the Status register.
B. Fetch the sequence repeat count.
C. If the sequence repeat count is zero, the sequence is
complete so reset the Using Sequencer bit and re-
turn to the Idle state, otherwise fetch the next vector
number and its repeat count.
D. If the vector number is zero, decrement the se-
quence repeat count and return to Step 3c. If the
vector number is illegal, i.e., other than 001, 010,
011, or 100, decrement the sequence repeat count
and return to Step 3c.
E. If the vector repeat count is equal to zero, fetch the
next vector number and its repeat count and go to
Step 3d. If the repeat count is non-zero fetch the
vector structure.
F. If the pre-load bit in the vector structure is not set,
reset the Using Sequencer bit and return to the Idle
state.
If the sequencer is not enabled but a vector is enabled
(the Use Vector bits in the Start register are non-zero),
fetch the current vector structure and set the appropriate
Using Vector bits in the Status register. If neither the
sequencer nor a vector is enabled, return to the Idle
state.
Fetch the Macro Structure to be used, set the vector/
macro control bits and store the TMS_SM bits in the
Structure Control registers.
If the Pre-shift TCK_SM Count is not zero, then enable
TCK_SM and drive TMS_SM using the first seven bits of
the macro until the Pre-shift TCK_SM Count is zero.
During pre-shift, TDO_SM will be driven with it’s previ-
ous value.
If the macro type is State then,
A. If the Macro Structure Bit 7 is enabled, set TMS_SM
to the bit 7 value of the macro structure and drive
TDO_SM with it’s previous value.
B. If the Macro Structure Bit 8 is enabled, set TMS_SM
to the bit 8 value of the macro structure and drive
TDO_SM with it’s previous value and then go to Step
10.
C. If the sequencer is being used then, decrement the
vector repeat count and return to Step 3e. If a vector
is being used, return to the Idle state.
If the macro type is BIST then,
A. If the Macro Structure Bit 7 is enabled, set the count
length, set TMS_SM to the bit 7 value of the macro
structure and drive TDO_SM with the default value
(Setup register bit 6) until the count length is zero.
B. If the Macro Structure Bit 8 is enabled, set TMS_SM
to the bit 8 value of the macro structure and drive
TDO_SM with the default value (Setup register bit 6)
and then go to Step 10.
C. If the sequencer is being used then, decrement the
vector repeat count and return to Step 3e. If a vector
is being used, return to the Idle state.
3.
4.
5.
6.
7.
8.
S
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