- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376340 > SCANSTA101 (National Semiconductor Corporation) RES 30K OHM 1/16W 0.1% 0402 SMD PDF資料下載
參數(shù)資料
| 型號： | SCANSTA101 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | RES 30K OHM 1/16W 0.1% 0402 SMD |
| 中文描述： | 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn) |
| 文件頁數(shù)： | 10/31頁 |
| 文件大?。?/td> | 403K |
| 代理商： | SCANSTA101 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
TABLE 8. Header / Trailer Usage
(Continued)
Function
Use Instruction Header
Use Instruction Trailer
Use both Instruction Header and Trailer
Use Data Header
Use Data Trailer
Use both Data Header and Trailer
Reserved
Bit 2
0
0
0
1
1
1
1
Bit 1
0
1
1
0
0
1
1
Bit 0
1
0
1
0
1
0
1
TABLE 9. Macro Type bits 10 and 11
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function
BIST Macro
Shift Macro
Function
Loop on loop bit for Vector count. No Data
Loop on loop bit for vector count. Read data from TDO_SM memory
Loop on loop bit for vector count. Read data from TDO_SM memory
Do not loop on loop bit of macro. No data to be shifted
Shift Macro with Capture
State Macro
TABLE 10. Sequencer Structure
Bit(s)
Function
Sequence repeat count (up to 255)
Vector repeat count
Vector number
Repeat vector repeat count and vector number
Vector repeat count (up to 255)
Vector number (up to 63)
0x00 - 0x1F
0x20 - 0x2F
0x30 - 0x3F
..x.. - ..x..
0x3E0 - 0x3EF
0x3F0 - 0x3FF
TABLE 11. Scan Bridge Support Structure
Bit(s)
Function
Levels of Scan Bridge support to be inserted in the scan chain
Hierarchical Level 0 Scan Bridge Address
Hierarchical Level 0 Scan Bridge LSP
Hierarchical Level 1 Scan Bridge Address
Hierarchical Level 1 Scan Bridge LSP
Hierarchical Level Scan Bridge Address and LSP
Hierarchical Level 125 Scan Bridge Address
Hierarchical Level 125 Scan Bridge LSP
0x00 - 0x0F
0x10 - 0x17
0x18 - 0x1F
0x20 - 0x27
0x28 - 0x2F
..x.. - ..x..
0x7F0 - 0x7F7
0x7F8 - 0x7FF
Module Descriptions
Figure 1
shows a high level view of the STA101 which is
composed of two main modules, the Parallel Processor In-
terface (PPI) and the Serial Scan Interface (SSI) which
interface to each other through a dual-port memory. The PPI
provides a parallel interface for transferring data into and out
of the dual-port memory, and for configuring, controlling and
obtaining the status of the device. The SSI which resides on
the other side of the dual-port memory provides the parallel-
to-serial and serial-to-parallel conversion paths for providing
test data and test control to support the ScanMaster and
IEEE 1532 functions.
Dual Port Memory
The dual port memory will be treated as a separate module
in the design to facilitate portability of the RTL of the design
to an FPGA host. The Dual Port Memory module is a 2048 x
32 bit dual-port memory which acts as the buffer between
the PPI and the SSI. There are seven regions of memory as
viewed from the processor side. These regions, shown in
Table 4
, are TDO_SM, TDI_SM, Expected, Mask, Vector,
Header/Trailer, Macro. Sequencer, and ScanBridge Support.
Each has a pointer which resides in the PPI.
The memory is big endian oriented and is viewed as a single
entity from the SSI side and the SSI maintains a pointer. The
dual port memory module does not include any logic outside
of its own macro function, so all the timing and support logic
is included in the following PPI and SSI sections. There will
be no logic included in the STA101 design to utilize the
"busy" indicators to keep the user from overwriting memory
locations. The only area were this could occur in memory
would be the TDI_SM memory space since both the SSI and
PPI can write to this space, but the drivers shouldn’t allow
PPI writes to this area during normal operations.
S
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANSTA111SM | EMITTER IR 850NM 5MM RADIAL |
| SCANSTA111 | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| SCANSTA111MT | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| SCANSTA112 | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA112SM | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 制造商:Texas Instruments 功能描述:Test Master IC |
| SCANSTA101SMX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。