參數(shù)資料
型號: SCANSTA101
廠商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁數(shù): 19/31頁
文件大小: 403K
代理商: SCANSTA101
Serial Scan Interface
(Continued)
cated by a "new data" pulse. On the same SCK rising edge
when the "new data" is detected to be high, the Start or
Setup register contents will be updated with new data. So,
the decoding of the enables takes place during the next
clock cycle to determine whether to process the sequencer
or a vector. Therefore, one clock after the "new data" is
detected, the SSIC starts loading the pointer register on
consecutive cycles with the appropriate addresses to fetch
the Sequencer, Vector and Macro Structures. Once the
headers are decoded and Structure Control Registers are
set up, the SSIC loads the pointer register so that data from
the TDO_SM memory area is fetched and loaded into the
TDO_SM shifter before being shifted out. However if there
are any sync bits and/or header bits and/or ScanBridge
support is enabled, then the sync bits and/or header bits
and/or ScanBridge pre-PAD bits will be loaded into the
TDO_SM shifter before processing the actual test vector.
Once the actual test vector is completely shifted out, again
depending on the ScanBridge support and/or the use of
trailers, post-PAD bits and the trailer bits are loaded and
shifted out through the TDO_SM shifter.
The count length will be decremented by one with each shift.
After shifting out all the current shifter contents the shifter will
be loaded with new data before the falling edge of the next
TCK_SM, if the count length is not exhausted. In the case
where data cannot be loaded from the memory before the
next falling edge of TCK_SM, the TCK_SM will be gated until
the data is available.
WRITING AND READING PARTIAL LONG WORDS
Care should be taken when writing a partial long word to
TDO_SM memory or reading a partial long word from
TDI_SM memory. Since the TDO_SM shifter shifts out LSB
first, the valid (meaningful) bits within a partial long word
(i.e., long word containing less than 32 valid bits to be shifted
to the scan chain) must be stored and written into the
memory as the least significant bits. This will assure that the
desired bits will be accurately loaded into the TDO_SM
shifter and shifted out to the boundary scan chain. For
instance, to shift a 3-bit (110) sequence the partial long word
should be written to the TDO_SM memory as shown in
Figure 9
(only the least significant 16 bits are shown). A
subsequent enable and load of the vector structure with the
correct length will initialize the shift operation and only the
bits that are significant will be shifted out to the scan chain.
Data is shifted from the scan chain into the TDI_SM shifter
from MSB to LSB. Consequently, the valid (i.e., meaningful)
bits in a partial long word shifted into the TDI_SM shifter will
reside in the upper significant bit locations. For example, if a
scan operation involves shifting and evaluating 69 bits re-
turning to TDI_SM, the TDI_SM memory will be loaded with
two long words (i.e., two full long words plus a partial long
word containing 5 meaningful bits). If the last 5 bits shifted
back to the TDI_SM shifter are 11010, then upon completion
of the shift operation, the TDI_SM shifter will contain the
following partial long word as shown in
Figure 10
(only most
significant 16 bits are shown), which will subsequently be
loaded into the TDI_SM memory.
10121534
FIGURE 8. Timing from Mode Register to Sequencer Start
10121535
FIGURE 9. Writing a Partial Long Word to the TDO_SM Memory
S
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