參數(shù)資料
型號(hào): SCANSTA101
廠(chǎng)商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù): 13/31頁(yè)
文件大小: 403K
代理商: SCANSTA101
Serial Scan Interface
(Continued)
The TAP Tracker will enter Test-Logic Reset state upon
setting the TRST bit (bit 5) in the Setup register or by issuing
a sequence of five TMS_SM high bits.
SHIFTER
The Shifter block contains two 32-bit shift registers for
TDO_SM and TDI_SM respectively, and one 16-bit shift
register for TMS_SM. The TMS_SM shifter block diagram is
shown in
Figure 2
, the TDO_SM shifter block diagram is
shown in
Figure 3
, and the TDI_SM shifter block diagram is
shown in
Figure 4
.
Before the start of a vector processing the TMS_SM shifter is
loaded with the least significant 16 bits of the macro struc-
ture. Based on the pre-shift TCK_SM count, the TMS_SM
shifter will skip (7 - pre-shift count) least significant bits. e.g.,
if the pre-shift count is 4, the least significant 3 bits of the
TMS_SM shifter will not be used to drive TMS_SM during
pre-shift. Similarly, if the post-shift is less than 7 then, during
post shift only the number of bits equal to the post-shift count
following the macro structure bit 8 will be used to drive
TMS_SM.
The STA101 memory is organized in big Endian format.
Since a memory write can be accomplished by two consecu-
tive writes to the same location when embedded software
loads the TDO_SM memory, it is assumed that the least
significant 16 bits are written first and then the most signifi-
cant 16 bits. Therefore, when the Sequencer or a Vector is
initialized the SSIC can directly fetch and load the long word
to the TDO_SM shifter without any modification.
Similarly, reading from TDI_SM memory can be accom-
plished by two consecutive reads. When reading from the
TDI_SM memory, the first read will contain the least signifi-
cant 16 bits and the second read the most significant 16 bits.
10121521
FIGURE 2. TMS_SM Shifter
10121522
FIGURE 3. TDO_SM Shifter
S
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