參數(shù)資料
型號(hào)： SCANSTA101
廠商： National Semiconductor Corporation
英文描述： RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述： 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù)： 11/31頁(yè)
文件大?。?/td> 403K
代理商： SCANSTA101
Parallel Processor Interface
The overall function of the PPI is to receive the parallel data
from the processor interface, store the data in its appropriate
register or memory location, act on the data if the data are
PPI control data, provide status data back to the processor
and to provide a read path for result data to the processor. To
perform these functions, the PPI consists of seven main
blocks of logic along with the dual-port memory. These
blocks include the Edge Detector (ED), Processor Interface
Controller (PIC), the Memory/ Register Decoder (MRD), the
Word/Long Word Converter (WLWC), the Control Generator
(CG), the Status/Interrupt Generator (SIG) and the Flag
Generator (FG).
WORD/LONG WORD CONVERTER
The Word/Long Word Converter (WLWC) has four 16-bit
capture registers, and least significant/ most significant (LS/
MS) word read capture register pair and an LS/MS word
write capture register pair. Each register within the write
register pair has a separate enable to allow for the neces-
sary control to accomplish word to long word conversions
when in the 16-bit mode. In 32-bit mode, these enables will
be driven simultaneously. A mux is provided in front of the
MS word register for the write capture to select between the
32-bit and 16-bit mode external bus. Only one enable and a
mux select is needed to control the read capture register pair
to accomplish the long word to word conversions when in the
16- bit mode. In the 32-bit mode, the mux selection doesn’t
change so 32-bits are always driven. A mux is on either side
of the LS word register for the read capture. The one at the
register output provides for selection between the 32-bit
and16-bit mode. The one at the register input is for selection
between register space and memory space. All the control
for this block is provided by the PIC and MRD with the 16/32
bit mode enable coming from the Setup register.
EDGE DETECTOR
The PPI module can support either an asynchronous or
synchronous processor interface. For an asynchronous in-
terface the circuit initially synchronizes STB and CE to the
system clock, SCK, by pipelining these two signals through
two flip-flop stages and then performs an edge detection on
STB and CE. For a synchronous parallel processor interface
this circuit just performs an edge detection. The outputs of
this circuit, one clock wide pulses indicating the detection of
negative and positive edges, will be used by the Processor
Interface Controller (PIC) state machine to start and to end a
processor access.
PROCESSOR INTERFACE CONTROLLER
The Processor Interface Controller (PIC) monitors the in-
coming processor control signals and sets up the appropri-
ate internal control signals to move the data into memory or
an internal register on a write or to move the data out of
memory or out of an internal register on a read. The PIC
edge detects the CE and the STB to start the access. The
PIC provides the control for the word to long word conver-
sion in the WLWC by controlling the three enables and the
mux select (READ_MSW) to the capture registers. The PIC
also controls when the internal read/write enable is issued to
the memory to complete the read/write operation. Timing for
register and memory read and write operations is described
in
PPI INTERFACE TIMING
.
MEMORY/REGISTER DECODER
The Memory/Register Decoder (MRD) contains all six index
registers (Index, Vector Index, Header/Trailer Index, Macro
Index, Sequencer Index and ScanBridge Support Index) and
four address registers (TDI_SM Address, TDO_SM Address,
Expected Address and Mask Address). In general, both in-
dex and address registers are used to maintain pointers to
their respective memory spaces. The exception is the Index
register which is used to set values in the four address
registers, i.e., writing to the Index register sets each of the
address registers. The value written to each address register
is the sum of its base address and the value written to the
Index register (the offset). All index and address registers,
with the exception of the Index register, will auto-increment
with each access to the corresponding memory space.
The MRD provides the address decode to generate all the
control and status register enables for the CG and the SIG.
The MRD also provides the mux selects for the register or
memory selection for the read capture operation in the
WLWC.
CONTROL GENERATOR
The Control Generator has the seven control registers within
it. The Start, Interrupt Control, Setup, Clock Divider, TDI_SM
LFSR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM
LFSR MSB Seed registers are all within this block. The CG
will issue a strobe to the SSI when a write has been issued
to the Start or Setup registers so the SSI can react to the
new control data. The strobe will be derived from edge
detecting the enables to the Start or Setup registers. The
"new" data to the SSI are the Use Sequencer bit and three
Use Vector bits from the Start register, and the TDO Default
Value, TRST, ScanBridge Support Initiate/Release, three
Sync Bit Length, and two Test Loop-back bits from the Setup
register.
STATUS/INTERUPT GENERATOR
The Status/Interrupt Generator has the four status registers
plus the logic to generate the interrupts and clear the inter-
rupts on a read. The registers are the Status, Interrupt
Status, TDI_SM LSFR LSB Result and TDI_SM LFSR MSB
Result registers. The SIG receives the LFSR result and
strobe signal SSI_LFSR_EN from the SSI and captures the
data in the LSB and MSB registers. The SIG receives the
compare result bit value from the SSI along with the com-
pare result bit clear and the compare result bit load.
The SIG receives the 4 memory space flags from the FG
along with their associated load and clear signals so these
bits may be constantly updated. The half-full, half-empty, full
and empty flags will be generated and updated regardless of
the states of their respective interrupt enables. The SIG also
receives the 4 interrupt enables for the flags. The SIG also
receives the sequencer active and 3 vector active signals
from the SSI. These will also be updated regardless of the
enable state.
If an interrupt enable is set then an interrupt will be gener-
ated. If an interrupt occurs at the same time as the interrupt
status is being read, then the interrupt will be set after the
read is complete. All bits in the Interrupt Status register are
cleared when the register is read.
FLAG GENERATOR
The FG takes in the TDI_SM or TDO_SM pointer values
from the PPI address pointers, compares them and gener-
ates the appropriate flags. If a flag condition has occurred, it
is passed along with the corresponding load enable to set
S
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SCANSTA101_06 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master
SCANSTA101SM 功能描述:接口 - 專(zhuān)用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA101SM/NOPB 功能描述:接口 - 專(zhuān)用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA101SM/NOPB 制造商:Texas Instruments 功能描述:Test Master IC
SCANSTA101SMX 功能描述:接口 - 專(zhuān)用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
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