參數(shù)資料
型號: SCANSTA101
廠商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁數(shù): 27/31頁
文件大?。?/td> 403K
代理商: SCANSTA101
Software Interface Details
(Continued)
TABLE 23. Setup Register (SETUPR) ($04)
Bit(s)
Type
Field
Address
Offset
0
0
0
0
0
0
0
0
0
0
Reset Value
Reset Source
15
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
16/32 bit Mode
Reserved
TDO_SM Ctrl
Sync Bit Length
Default TDO Value
Debug Mode
ScanBridge Support Initiate/ Release
TRST
Reset
Test Loop-Back
0b
00h
00b
000b
1b
0b
0b
0b
0b
11b
SYS_RST
14:10
11:10
9:7
6
5
4
3
2
1:0
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
16/32 bit Mode
Selects 16-bit or 32-bit external interface mode
32-bit external interface mode (used in macro form only)
16-bit external interface mode
TDO_SM Control bits
Hold previous value
Default TDO Value
Default TDO Value
High impedance
Sync Bit Length bits represents the number of sync bits to be used when the Sync Bit
Support Enable bit (17 in the Macro Structure) is set. Where "x" is the binary encoded
numeric value.
The value in this register will be sent out on the TDO_SM pin when performing a BIST
or a STATE Macro.
Drive TDO_SM to one.
Drive TDO_SM to zero.
Control bit to put STA101 in debug mode
Debug mode.
Normal mode.
ScanBridge support enable
’1’
’0’
TDO_SM Ctrl
<
11:10
>
’00’
’01’
’10’
’11’
Sync Bit Length "x"
Default TDO Value
’1’
’0’
Debug Mode
’1’
’0’
ScanBridge Support
Initiate/Release
’1’
’0’
Enable ScanBridge support
Disable ScanBridge support
Processor initiated ScanMaster test reset (on TRST0_SM and TRST1_SM_N). Bit is
cleared by a processor write.
Set TRST outputs low (active) and reset SSI logic.
Set TRST outputs high
Processor commanded synchronous reset to the serial scan logic for 2 clocks. This bit
is self clearing.
Reset the entire chip.
Release serial scan logic reset
Test loop-back mode bits
Normal operation
Loop-back TDO_SM to TDI_SM
Loop-back TMS_SM to TDI_SM
All Dot1 (1149.1) pins placed in SEU tolerant safe mode with: TMS_SM = 1, TCK_SM
= 0, TDO_SM = Z, TRST0_SM = 0
TRST
’1’
’0’
Reset
’1’
’0’
Test Loop-Back
<
1:0
>
’00’
’01’
’10’
’11’
S
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