參數(shù)資料
型號(hào): SCANSTA101
廠商: National Semiconductor Corporation
英文描述: RES 30K OHM 1/16W 0.1% 0402 SMD
中文描述: 低壓主STA的IEEE 1149.1標(biāo)準(zhǔn)
文件頁(yè)數(shù): 26/31頁(yè)
文件大?。?/td> 403K
代理商: SCANSTA101
Software Interface Details
(Continued)
Vector Interrupt Enable
<
2:0
>
Vector "x" complete interrupt enable, where "x" is the vector number, a binary
encoding of bits
<
2:0
>
. Only vector interrupts1 through 4 are valid. Vector interrupts 5
through 7 reserved for future use.
No vector interrupt enabled
Vector 1 interrupt enabled
Vector 2 interrupt enabled
Vector 3 interrupt enabled
Vector 4 interrupt enabled
’000’
’001’
’010’
’011’
’100’
TABLE 22. Interrupt Status Register (INTSTAT) ($03)
(Note 22)
Bit(s)
Type
Field
Address
Offset
0
0
0
0
0
0
0
Reset Value
Reset Source
15:13
12
11
10
9
8
7:3
RO
RW
RW
RW
RW
RW
RO
Reserved
TDO Half-empty Interrupt (Note 21)
TDO Empty Interrupt
TDI Full Interrupt
TDI Half-full Interrupt (Note 21)
Sequencer Interrupt
Reserved Vector x Interrupt (Notes
19, 20)
Vector x Interrupt (Note 20)
00b
0b
1b
0b
0b
0b
00000b
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
2:0
RW
0
000b
SYS_RST
Note 19:
Reserved Vector x Interrupt for future growth for the number of vectors.
Note 20:
Drivers shouldn’t allow Sequencer Interrupt and Vector x Interrupt to be set at same time. Sequencer Interrupt has priority over the Vector x Interrupt.
Note 21:
Half full or half empty designates 56 long words.
Note 22:
This register is writable in debug mode only.
TDO Half-empty Interrupt
TDO_SM memory space half empty status
TDO_SM memory space half empty
TDO_SM memory space not half empty
TDO_SM memory space empty status
TDO_SM memory space empty
TDO_SM memory space not empty
TDI_SM memory space full status
TDI_SM memory space full
TDI_SM memory space not full
TDI_SM memory space half full status
TDI_SM memory space half full
TDI_SM memory space not half full
Sequencer completed status
Sequencer processing completed
Sequencer processing or not started
Vector "x" completed status, where "x" is the vector number, a binary encoding of bits
<
2:0
>
.Only vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future use.
No vector completed activity
Vector 1 completed
Vector 2 completed
Vector 3 completed
Vector 4 completed
’1’
’0’
TDO Empty Interrupt
’1’
’0’
TDI Full Interrupt
’1’
’0’
TDI Half-full Interrupt
’1’
’0’
Sequencer Interrupt
’1’
’0’
Vector Interrupt
<
2:0
>
’000’
’001’
’010’
’011’
’100’
S
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