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參數(shù)資料
| 型號： | SCANSTA101 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | RES 30K OHM 1/16W 0.1% 0402 SMD |
| 中文描述： | 低壓主STA的IEEE 1149.1標準 |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 403K |
| 代理商： | SCANSTA101 |
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Serial Scan Interface
(Continued)
Following a read of a partial long word, the embedded test
software must adjust the position of the valid bits read from
the TDI_SM shifter/buffer or the position of the expected
data to assure that an accurate comparison is made (and the
non-meaningful bits are masked).
TDO_SM IMPLEMENTATION
The behavior of the TDO_SM output depends on the current
macro type that is being processed and the SETUP register
bits 11 and 10, as shown in
Table 13
, regardless of the TAP
tracker state. For shift macros, the TDO_SM output also
depends on the current macro structure’s TMS_SM bit num-
ber as explained below.
TABLE 13. TDO_SM Output Behavior
SETUP[11:10]
00
01 or 10
11
TDO_SM
Hold Previous value
Default TDO value (Bit 6 of the SETUP register) (Note 10)
High Impedance
Note 10:
Default TDO value (bit 6 of the SETUP register) may be set to a 0 when SETUP[11:10]=01 and to a 1 when SETUP[11:10]=10.
For BIST and STATE macros, the TDO_SM output behaves
exactly as shown in the above table, however, for the shift
macros, with or without capture, the TDO_SM output be-
haves as per the table only when the corresponding
TMS_SM output is not driven by the macro structure bit 7 or
8. On each falling edge of the TCK_SM following the
TCK_SM’s falling edge on which the TMS_SM changes
state from bit 6 of the macro structure to the bit 7of the macro
structure, the serial test vector data fetched from the
Hardware Interface Details
memory will be presented on the TDO_SM output. On the
falling edge of the TCK_SM on which the final bit of the test
vector is presented on the TDO_SM output, the TMS_SM
will be presented with the macro structure bit 8. On the
consequent TCK_SM falling edges and on the TCK_SM
falling edges before the TMS_SM changes state from bit 6 to
bit 7 of the macro structure the TDO_SM will behave as per
the table above.
TABLE 14. System Interface Signal Description
Signal Name
No. of
Bits
1
Pin Type
Driver Type
Freq.
MHz
66
Description
SCK
I
LVTTL
System Clock: This is the main clock signal to the STA101.
SCK is used to clock all internal circuitry
Hardware Reset signal (with hysteresis (H)): This is the
STA101 asynchronous reset signal.This signal resets the
entire STA101 and sets all registers to their respective
default values.
Output enable: Tristates all dot1 outputs when high.
RST
1
I,H
LVTTL
N/A
OE
1
I
LVTTL
N/A
TABLE 15. Parallel Processor Interface Signal Descriptions
Signal Name
No. of
Bits
16
Pin Type
Driver Type
Freq.
MHz
N/A
Description
DATA(31:16)
I/O
LVTTL
(weakest
driver)
LVTTL
LVTTL
Bidirectional Data Bus. Not bonded out in packaged part.
These are only used in the 32-bit macro version.
DATA(15:0)
ADDRESS(4:0)
16
5
I/O
I
N/A
N/A
Bidirectional Data Bus.
Address Bus
10121536
FIGURE 10. Reading a Partial Long Word from the TDI_SM Memory
S
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 制造商:Texas Instruments 功能描述:Test Master IC |
| SCANSTA101SMX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
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