
IX PERIPHERAL MODULES 7 (USB): USB FUNCTION CONTROLLER (USB)
S1C33E07 TECHNICAL MANUAL
EPSON
IX-1-5
IX
USB
3. Setting the HSDMA
Setting the address mode
The HSDMA circuit provides two data transfer mode: dual-address transfer and single-address transfer
modes. The USB function controller supports only the dual-address mode. In this mode, a source address and
a destination address for DMA transfer can be specified and a DMA transfer is performed in two phases. The
first phase reads data at the source address into the on-chip temporary register. The second phase writes the
temporary register data to the destination address.
To configure HSDMA Ch.1 in this mode, set DUALM1 (D15/0x301132) to 1.
Note: Do not set the HSDMA Ch.1 to single-address mode when using it for USB data transfer.
Setting the transfer mode
The USB function controller supports two transfer modes, asynchronous multi-word DMA transfer (slave)
mode and asynchronous single-word DMA transfer (slave) mode.
The asynchronous multi-word DMA transfer (slave) mode asserts the PDREQ signal while the USB FIFO
contains data. The CPU cannot determine the amount of data in the FIFO to be transferred in a DMA
transfer while the USB is sending/receiving data dynamically (since data in the FIFO is increased/decreased
dynamically according to the circumstances of the USB data transfer).
Therefore, set the USB function controller to asynchronous single-word DMA transfer (slave) mode and the
HSDMA to single transfer mode with one byte transfer per trigger, and manage the DMA transfer count with
the total amount of USB transfer data.
To set the HSDMA into single transfer mode, set D1MOD[1:0] (D[15:14]/0x30113A) to 00. In this mode,
a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by
DATSIZE1. If data transfer need to be performed a number of times as set by the transfer counter, an equal
number of triggers are required.
Setting the transfer data size
DATSIZE1 (D14/0x301136) is used to set the unit size of data to be transferred. Set this bit to 0 (8 bits).
Setting the transfer counter
In the single transfer mode, up to 24 bits of transfer count can be specified using the registers below. Set the
desired transfer count to these registers.
BLKLEN1[7:0]: Ch.1 transfer counter [7:0] (D[7:0])/HSDMA Ch.1 Transfer Counter Register (0x301130)
TC1_L[7:0]:
Ch.1 transfer counter [15:8] (D[15:8])/HSDMA Ch.1 Transfer Counter Register (0x301130)
TC1_H[7:0]:
Ch.1 transfer counter [23:16] (D[7:0])/HSDMA Ch.1 Control Register (0x301132)
Note: The transfer count thus set is decremented according to the transfers performed. If the transfer
count is set to 0, it is decremented to all Fs by the first transfer performed. This means that you
have set the maximum value that is determined by the number of bits available.
Setting the source and destination addresses
In dual-address mode, a source address and a destination address for DMA transfer can be specified using the
registers below.
S1ADRL[15:0]: Ch.1 source address [15:0] (D[15:0])/HSDMA Ch.1 Low-order Source Address Set-up
Register (0x301134)
S1ADRH[11:0]: Ch.1 source address [27:16] (D[11:0])/HSDMA Ch.1 High-order Source Address Set-up
Register (0x301136)
D1ADRL[15:0]: Ch.1 destination address [15:0] (D[15:0])/HSDMA Ch.1 Low-order Destination Address Set-
up Register (0x301138)
D1ADRH[11:0]: Ch.1 destination address [27:16] (D[11:0])/HSDMA Ch.1 High-order Destination Address
Set-up Register (0x30113A)
Note: The DMA transfer address for the USB function controller must be located in Area 6 (0x300A00
to 0x300AFF, 256 bytes). Make sure that the transfer address does not exceed the address range
from 0x300A00 to 0x300AFF by the address increment/decrement operation during DMA transfer.