
II BUS MODULES: HIGH-SPEED DMA (HSDMA)
S1C33E07 TECHNICAL MANUAL
EPSON
II-1-5
II
HSDMA
II.1.2 I/O Pins of HSDMA
Table II.1.2.1 lists the I/O pins used for HSDMA.
Table II.1.2.1 I/O Pins of HSDMA
Pin name
#DMAREQ0
#DMAREQ1
#DMAREQ2
#DMAREQ3
#DMAACK0
#DMAACK1
#DMAACK2
#DMAACK3
#DMAEND0
#DMAEND1
#DMAEND2
#DMAEND3
I/O
I
O
Function
DMA transfer request input pin for HSDMA Ch.0
DMA transfer request input pin for HSDMA Ch.1
DMA transfer request input pin for HSDMA Ch.2
DMA transfer request input pin for HSDMA Ch.3
DMA acknowledge signal output pin for HSDMA Ch.0
DMA acknowledge signal output pin for HSDMA Ch.1
DMA acknowledge signal output pin for HSDMA Ch.2
DMA acknowledge signal output pin for HSDMA Ch.3
End-of-transfer signal output pin for HSDMA Ch.0
End-of-transfer signal output pin for HSDMA Ch.1
End-of-transfer signal output pin for HSDMA Ch.2
End-of-transfer signal output pin for HSDMA Ch.3
#DMAREQx (DMA request input pin)
This pin is used to input a DMA request signal from an external peripheral circuit. One data transfer opera-
tion is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). The
#DMAREQ0 to #DMAREQ3 pins correspond to channel 0 to channel 3, respectively.
In addition to this external input, software trigger or a cause of interrupt can be selected for the HSDMA trigger
source using the register in the interrupt controller.
#DMAACKx (DMA acknowledge signal output pin)
This signal is output to indicate that a DMA request has been acknowledged by the DMA controller.
In single-address mode, the I/O device that is the source or destination of transfer outputs data to the external
bus or takes in data from the external data synchronously with this signal.
The #DMAACK0 to #DMAACK3 pins correspond to channel 0 to channel 3, respectively.
This signal is also output in dual-address mode.
See Figures II.1.1.2, II.1.1.3 and II.1.1.5 for the waveform of the #DMAACKx signal.
#DMAENDx (End-of-transfer signal output pin)
This signal is output to indicate that the number of data transfer operations that is set in the control register have
been completed. The #DMAEND0 to #DMAEND3 pins correspond to channel 0 to channel 3, respectively.
Note: The control pins above are shared with general-purpose input/output ports or other peripheral
circuit input/output pins, so that functionality in the initial state is set to other than the HSDMA. Be-
fore the HSDMA signals assigned to these pins can be used, the functions of these pins must be
switched for the HSDMA by setting each corresponding Port Function Select Register.
For details of pin functions and how to switch over, see Section I.3.3, “Switching Over the Multi-
plexed Pin Functions.”