
II BUS MODULES: HIGH-SPEED DMA (HSDMA)
S1C33E07 TECHNICAL MANUAL
EPSON
II-1-27
II
HSDMA
Address
0x00301162
0x00301164
0x00301166
0x00301168
0x0030116A
0x00301172
0x00301174
0x00301176
0x00301178
0x0030117A
0x00301182
0x00301184
0x00301186
0x00301188
0x0030118A
0x00301192
0x00301194
0x00301196
0x00301198
0x0030119A
0x0030119C
0x0030119E
Function
Selects Ch.0 ADV mode functions.
Sets Ch.0 low-order source address for ADV mode.
Sets Ch.0 high-order source address for ADV mode.
Sets Ch.0 low-order destination address for ADV
mode.
Sets Ch.0 high-order destination address for ADV
mode.
Selects Ch.1 ADV mode functions.
Sets Ch.1 low-order source address for ADV mode.
Sets Ch.1 high-order source address for ADV mode.
Sets Ch.1 low-order destination address for ADV
mode.
Sets Ch.1 high-order destination address for ADV
mode.
Selects Ch.2 ADV mode functions.
Sets Ch.2 low-order source address for ADV mode.
Sets Ch.2 high-order source address for ADV mode.
Sets Ch.2 low-order destination address for ADV
mode.
Sets Ch.2 high-order destination address for ADV
mode.
Selects Ch.3 ADV mode functions.
Sets Ch.3 low-order source address for ADV mode.
Sets Ch.3 high-order source address for ADV mode.
Sets Ch.3 low-order destination address for ADV
mode.
Sets Ch.3 high-order destination address for ADV
mode.
Selects standard or advanced mode.
Sets sequential access time for IDMA and HSDMA.
Register name
HSDMA Ch.0 Control Register (pHS0_ADVMODE) for
ADV mode
HSDMA Ch.0 Low-Order Source Address Setup Register
(pHS0_AD_SADR) for ADV mode
HSDMA Ch.0 High-Order Source Address Setup
Register for ADV mode
HSDMA Ch.0 Low-Order Destination Address Setup
Register (pHS0_ADV_DADR) for ADV mode
HSDMA Ch.0 High-Order Destination Address Setup
Register for ADV mode
HSDMA Ch.1 Control Register (pHS1_ADVMODE) for
ADV mode
HSDMA Ch.1 Low-Order Source Address Setup Register
(pHS1_AD_SADR) for ADV mode
HSDMA Ch.1 High-Order Source Address Setup
Register for ADV mode
HSDMA Ch.1 Low-Order Destination Address Setup
Register (pHS1_ADV_DADR) for ADV mode
HSDMA Ch.1 High-Order Destination Address Setup
Register for ADV mode
HSDMA Ch.2 Control Register (pHS2_ADVMODE) for
ADV mode
HSDMA Ch.2 Low-Order Source Address Setup Register
(pHS2_AD_SADR) for ADV mode
HSDMA Ch.2 High-Order Source Address Setup
Register for ADV mode
HSDMA Ch.2 Low-Order Destination Address Setup
Register (pHS2_ADV_DADR) for ADV mode
HSDMA Ch.2 High-Order Destination Address Setup
Register for ADV mode
HSDMA Ch.3 Control Register (pHS3_ADVMODE) for
ADV mode
HSDMA Ch.3 Low-Order Source Address Setup Register
(pHS3_AD_SADR) for ADV mode
HSDMA Ch.3 High-Order Source Address Setup
Register for ADV mode
HSDMA Ch.3 Low-Order Destination Address Setup
Register (pHS3_ADV_DADR) for ADV mode
HSDMA Ch.3 High-Order Destination Address Setup
Register for ADV mode
HSDMA STD/ADV Mode Select Register
(pHS_CNTLMODE)
DMA Sequential Access Time Register (pHS_ACCTIME)
Size
16
The following describes each HSDMA control register.
The HSDMA control registers are mapped in the 16-bit device area from 0x301120 to 0x30119E, and can be ac-
cessed in units of half-words or bytes.
Note: When setting the HSDMA control registers, be sure to write a 0, and not a 1, for all “reserved bits.”