- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361226 > Q6701-H6481 (SIEMENS AG) Quadruple Transceiver for S/T Interface QUAT-S PDF資料下載
參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 57/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當(dāng)前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
PEB 2084
Semiconductor Group
57
4.4
Read/Write, Address: 4
H
Auxiliary Register
Initial value: CI(3:0), 0
H
Note:
Register bits not described may exist in hardware due to the use of PEB 2081,
SBCX, core. Writing those bits other than the default value will cause unexpected
behavior of the device.
bit 7
CI3
bit 0
DCM0
Format:
CI2
CI1
CI0
TOD
0
DCM1
Bit-name
CI(3:0)
Description
C/I codes as in C/I channel
The indication can be read via monitor channel CI (3:0).
Time-Out Disable
0:
Monitor timeout (minimum 5 ms)
1:
The time-out function of the monitor transmitter can be disabled
to ease manual software debugging.
D-channel mode:
Specific D channel associated functions including the pins DRDY and
CEB/SSYNC:
00: Transparent D-channel, pins DRDY and CEB/SSYNC tristated.
10: LT-T mode:
D-channel collision resolution according to CCITT
I.430. Pin DRDY conveys control information
synchronous to D-channel timeslots to control
PEB 2075, IDEC (0: stop; 1: go).
LT-S mode:
D-channel access control by establishing a logical
passive bus structure, where the received D-channel is
ANDed with the other channels selected over pin
CEB and the resulting value is sent back as Echo bit.
11: LT-T mode:
D-channel collision resolution according to CCITT
I.430. Pin DRDY conveys asynchronous control
information to control SACCO-B in the ELIC,
PEB 20550. This mode is only applicable for a single
channel LT-T application (0: go; 1: stop).
LT-S mode:
D-channel access control via the central D-channel
arbiter unit of the PEB 20550, ELIC. Dependent on
the command, each channel mirrors the received
D-channel into the Echo channel inverted
command 1100
H
) or unchanged (1000
H
).
01: Not applicable
TOD
DCM(1:0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67020-Y149 | Octal Latch |
| Q67020-Y150 | Octal Latch |
| Q67020-Y151 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | OCTAL BUS TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y151 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。