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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 27/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
27
In the receive direction two cases have to be distinguished depending on the bus
configuration:
–
Short passive bus configuration
(Configuration Register: C/W = 1)
The 192 kHz receive bit clock is identical to the transmit bit clock. The sampling instant
for the receive bits is shifted by 4.6
μ
s with respect to the transmit bit clock. According to
CCITT I.430 the receive frame shall be shifted (delayed) by two bits with respect to the
transmit frame.
–
Point-to-point or extended passive bus configurations
(Configuration Register: C/W = 0)
The 192 kHz receive bit clock is recovered (via PLL) from the receive data stream on the
S interface. According to CCITT I.430 the receive frame can be shifted by 2 to 8 bits with
respect to the transmit frame. However other shifts are allowed by the QUAT-S as well;
including 0.
LT-T Mode
(Configuration Register: Mode = 1)
In LT-T applications the QUAT-S is a clock slave to the central office clock, which is
always the master. Thus a PBX clock system must be locked up with the CO clock
system.
The 192 kHz receive bit clock is recovered (via PLL) from the receive data stream on the
T interface.
2.3.3
The receive signal is sampled several times (oversampling) inside the receive clock
period, and a majority logic is used to reduce the bit error rate in severe conditions.
As illustrated in
figure 13
, each received bit is sampled 29 times at 7.68 MHz clock
intervals inside the estimated bit window. The samples obtained are compared against
a threshold of 50 % with respect to the signal stored by the peak detector. If at least 16
samples have an amplitude exceeding the set threshold, a logical “0” is considered to be
detected; otherwise a logical “1” (no signal) is considered to be detected.
Receive Signal Oversampling
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67020-Y149 | Octal Latch |
| Q67020-Y150 | Octal Latch |
| Q67020-Y151 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | OCTAL BUS TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y151 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
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