參數(shù)資料
型號(hào)： Q6701-H6481
廠商： SIEMENS AG
英文描述： Quadruple Transceiver for S/T Interface QUAT-S
中文描述： 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁數(shù)： 21/72頁
文件大?。?/td> 1267K
代理商： Q6701-H6481
PEB 2084
Semiconductor Group
21
2.2.3
The QUAT-S provides a boundary scan support for a cost effective board testing. It
consists of:
– Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1
specification
– Test access port controller (TAP)
– Four dedicated pins (TCK, TMS, TDI, TDO)
– One 32-bit IDCODE register
– Specific functions for SXna,b
JTAG Boundary Scan Test Interface
Boundary Scan
The following QUAT-S pins are included in the boundary scan:
FSC, DCL, IDI, IDO, RST, ICS, CEB, DRDY, CLK1, CLK2 and XTAL1.
Depending on the pin functionality one or two boundary scan cells are provided.
When the TAP controller is in the appropriate mode data is shifted into/ out of the
boundary scan via the pins TDI/TDO using the 6.25 MHz clock on pin TCK.
The QUAT-S pins are included in the boundary scan in the following sequence:
Pin Type
Input
Output
Number of Boundary Scan Cells
1
2
Usage
Input
Output, enable
Boundary Scan Number
TDI ––>
1
2
3
4
5
6
7
8
9
10
11
Pin Number
Pin Name
Type
Number of
Scan Cells
1
1
1
2+1
1
1
2 + 1
2
1
2
1 + 2
43
42
41
40
39
38
36
35
20
18
17
FSC
DCL
IDI
IDO
ICS
RST
CLK1/IDS
CLK2
XTAL1
DRDY
CEB/SSYNC
I
I
I
O
I
I
O/I
O
I
O
I/O
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