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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
32
3
All procedures required for data transmission over the S/T interface are implemented.
These comprise the S/T interface frame and multiframe synchronization,
activation/deactivation procedure, and timing requirements such as bit rate and jitter. For
a correct functionality of the QUAT-S the following operational precautions must be
taken:
Operational Description
3.1
At power up, a reset pulse (RST) should be applied to bring the line interfaces of the
PEB 2084, QUAT-S, to the state “reset”. No clocks are required during that procedure.
After that the PEB 2084, QUAT-S, may be operated according to the state diagram,
each line interface controlled via the corresponding C/I channel.
Reset
3.2
The QUAT-S senses whether an external pull-up resistor (100 k
to 1 M
) is connected
to the pin IDO. The sensing is done after reset within the following two IOM frames in the
monitor channel.
The pin is pulled low for one bit and then switched to tristate. If the voltage level at IDP0
rises in the next bit to “High”, QUAT-S interprets this behaviour as an external pull up
being connected to the pin and remains as open collector. If the level stays at “Low”
QUAT-S switches to push-pull. However, actions of other device on this line or crosstalk
from other lines during the sensing procedure may falsify the result. (A pull down resistor
of 100 k
to 1 M
may improve the correctness of the sensing). This feature is useful if
multiple transmitters are connected to the same IOM-2 interface, e.g. QUAT-S with an
IDEC.
Push – Pull Sensing on Pin IDO
3.3
IOM
-2 Interface
3.3.1
The allocation between S/T line interfaces and the IOM-2 ISDN channels is according to
their numbers with an offset of four or zero. The offset can be selected via pin ICS by pin
strapping, i.e.
for ICS = 0 the SRX0a,b is allocated to IOM channel 0, and so on,
for ICS = 1 the SRX0a,b is allocated to IOM channel 4, and so on.
For detailed electrical definition refer to the
chapter 5
and the IOM Interface
Specification, Rev. 2.
As described in
chapter 2.2.2
, each basic ISDN channel consists of five different
communication channels: two voice channels, one monitor channel (incl. MR and MX
bits), one D-channel and one command/indication (C/I) channel.
ISDN Channels Allocation
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