參數(shù)資料
型號(hào)： Q6701-H6481
廠商： SIEMENS AG
英文描述： Quadruple Transceiver for S/T Interface QUAT-S
中文描述： 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁數(shù)： 18/72頁
文件大?。?/td> 1267K
代理商： Q6701-H6481
PEB 2084
Semiconductor Group
18
Thus, depending on the programmable QUAT-S mode, the data lines IDI and IDO get
different meanings: IDI
(IOM interface Data Input)
= Data Downstream in LT-S
= Data Upstream
in LT-T
in LT-S
IDO (IOM-2 interface Data Output) = Data Upstream
= Data Downstream in LT-T
The data is clocked by Data Clock (DCL) that operates at single or double data rate. The
selection is done by pinstrapping (CLK1/IDS). The IOM frames are delimited by an 8 kHz
Frame Synchronization Clock (FSC). The FSC rising edge indicates the start of an
IOM
-
2 frame.
The IOM-2 interface specification describes open drain data lines with external pull-up
resistors. However, if operation is logically point-to-point, tristate operation is possible as
well.
Frame Structure
One IOM-2 frame typically contains 8 IOM channels (sub-frames). The ISDN user data
rate is 144 kbit/s (B1 + B2 + D). The data is transmitted transparently synchronously and
in phase in both directions over the IOM-2 interface using time division multiplexing
within the 125
μ
s IOM-2 interface frame.
Refer to
figure 7
.
QUAT-S requires IOM-2 frame consisting of n complete ISDN channels (with 32 bits per
channel); n = 4, 5, 6, … 16.
Nominal bit rate of data (IDI and IDO)
1024 kbit/s
Nominal frequency of DCL
2048 kHz
Selectable frequency of DCL
1024 kHz
Nominal frequency of FSC
8 kHz
… 4096 kbit/s
… 8192 kHz
… 4096 kHz
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