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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 26/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
26
Note:
The actual values of the external resistors depend on the selected transformer.
The resistor values are optimal for an ideal transformer (
R
Cu
= 0).
Line termination (
R
T
) is applied to the last TE on the S bus only.
The transmitter of the QUAT-S is identical to that of SBCX, hence the line interface
circuitry should be the same. The external resistors (20 … 40
) are required in order to
adjust the output voltage to the pulse mask (nominal 750 mV according to CCITT I.430)
on the one hand and in order to meet the output impedance of a minimum of 20
(transmission of a binary one according to CCITT I.430) on the other hand.
The QUAT-S has a symmetrical receiver.
Useful hints on how to design the external interface circuitry are contained in the
application note “S/T interface circuitry using the PEB 2080, SBC, or PEB 2085,
ISAC
-
S” from 12.89.
2.3.2
LT-S Mode
(Configuration Register: Mode = 0)
In the LT-S mode the QUAT-S is the clock master to all connected TEs.
The transmit PLL (XPLL) synchronizes the 192 kHz transmit bit clock to the IOM-2 clock
FSC (8 kHz) derived from the oscillator clock. When the oscillator clock is synchronous
to FSC (fixed divider ratio of 960 from 7.68 MHz clock) the XPLL will not perform any
tracking after having locked the phase, i.e. the input jitter on clocks XTAL and FSC will
not be increased,
see figure 12.
Timing Recovery
Figure 12
Block Diagram of XPLL
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| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
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| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
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