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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 53/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
53
All other S and Q bit positions within the remaining 12 frames of the multi-frame carry the
value ZERO.
The S and Q bits are accessed by the ELIC or EPIC via IOM-2 interface monitor channel.
The bits are handled in byte format packed in the lower nibble. The upper nibble is used
as identifier for the message type. The bit structure used by the QUAT-S is outlined in the
following table.
QUAT-S has implemented a 3
×
4 bit RAM as buffer for the S and Q bits. The 4-bit RAM
cells can be addressed separately.
The data are handled by the QUAT-S in either non auto mode or in transparent mode.
In the transparent mode the S data are transferred in downstream direction as a real time
data stream of 1.600 bit/s (8 bits in 5 ms = 20
×
250
μ
s), the Q data are transferred in
upstream direction as a real time data stream of 800 bit/s (4 bits in 5 ms).
In non auto mode the received S and Q channels are checked for code changes and, if
a change is detected, the new four bits are transferred. In transmit direction each of the
4-bit message is repeated until a new word is written into the buffer (e.g. into the MFFIFO
in ELIC).
3.7
The PEB 2084, QUAT-S, uses the input signal at pin CEB/SSYNC as an external
multiframe synchronization input in any case except if DCM(1:0) is set to “10” in any of
the four channels. The external multiframe synchronization input signal is expected to be
low for 125
μ
s and high for 2n + 1 times 125
μ
s thus defining an S/T interface multiframe
of n + 1 frames. The edges of the external multiframe synchronization input signal have
to be in coincidence with the rising edges of FSC. Each low at this input will generate one
frame with M-bit as binary ONEs at the S/T interface output. When setting bit MFD
(configuration register) to “1”, this function enables the generation of arbitrary
multiframes, which may be useful to synchronize digital cellular wireless
communications equipment.
While using SSYNC for M-bit generation the short FSC signal is not allowed as it would
reset the Super-Frame generated by SSYNC. If not used, the SSYNC input must be
connected via a pull-up resistor to
V
DD
.
Default-Use of Pin CEB/SSYNC
Identifier
0 0 0 1
0 0 1 0
0 0 0 1
Downstream Data
S11 S12 S13 S14
S21 S22 S23 S24
Upstream Data
Q1 Q2 Q3 Q4
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相關(guān)代理商/技術(shù)參數(shù) |
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| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
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| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
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