參數(shù)資料
型號: Q6701-H6481
廠商: SIEMENS AG
英文描述: Quadruple Transceiver for S/T Interface QUAT-S
中文描述: 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁數(shù): 30/72頁
文件大小: 1267K
代理商: Q6701-H6481
PEB 2084
Semiconductor Group
30
2.3.5.1 Multi-Frame Generation with a short FSC
The QUAT-S synchronizes to a multi-frame structure according to CCITT
recommendation I.430.
In
LT-S
application mode the S interface multi-frame (20
×
250
μ
s = 5 ms period) can be
generated by a master device (e.g. ELIC) by inserting a short FSC pulse.
An external strobe on the pin CEB/SSYNC can be used for simple terminal
synchronization.
A short FSC pulse has a width of one DCL clock whereas a normal FSC pulse has a
width of at least two DCL clocks. The QUAT-S samples the FSC input with the second
falling edge of DCL clock in the very first bit positions of the frame. If the sampled bit is
zero the S/T interface transmit frame, including multi-frame, is reset.
The frame relationship between IOM-2 interface (FSC) and S/T interface is shown in the
following figures.
Figure 15
Multi-Frame Generation with a Short FSC
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