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參數(shù)資料
| 型號(hào)： | PSD913F2 |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads |
| 中文描述： | 可配置的存儲(chǔ)系統(tǒng)級(jí)芯片的8位微控制器 |
| 文件頁數(shù)： | 9/94頁 |
| 文件大?。?/td> | 463K |
| 代理商： | PSD913F2 |
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PSD913F1
Preliminary
8
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD913F1 device can be programmed or
erased without the use of the microcontroller. The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out
of the EEPROM or SRAM. The EEPROM can be programmed the same way by executing
out of the main Flash memory. The PLD logic or other PSD913F1 configuration can be
programmed through the JTAG port or a device programmer. Table 4 indicates which
programming methods can program different functional blocks of the PSD913F1.
PSD913F1
Architectural
Overview
(cont.)
JTAG
Device
Programmer
In-System Parallel
Programming
Functional Block
Programming
Main Flash memory
Yes
Yes
Yes
EEPROM memory
Yes
Yes
Yes
PLD Array (DPLD and GPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Optional OTP Row
No
Yes
Yes
Table 4. Methods of Programming Different Functional Blocks of the PSD913F1
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD913F1 gives the user control of the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The PSD913F1 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off and
the GPLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the GPLD to reduce power consumption. See section 9.5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913F2V | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD934F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD913F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD934F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913F2-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2-12JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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