參數(shù)資料
型號: PSD913F2
英文描述: 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述: 可配置的存儲系統(tǒng)級芯片的8位微控制器
文件頁數(shù): 66/94頁
文件大?。?/td> 463K
代理商: PSD913F2
Preliminary
PSD913F1
65
AC/DC
Parameters
The following tables describe the AD/DC parameters of the PSD913F1 family:
J
DC Electrical Specification
J
AC Timing Specification
PLD Timing
Combinatorial Timing
Microcontroller Timing
Read Timing
Write Timing
Power Down and Reset Timing
Following are issues concerning the parameters presented:
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In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD913F1 is in each mode. Also, the supply power is considerably different if the
Turbo bit is "OFF".
J
The AC power component gives the PLD, Flash memory, EEPROM, and SRAM
mA/MHz specification. Figure 28 shows the PLD mA/MHz as a function of the number
of Product Terms (PT) used.
J
In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
Figure 28. PLD I
CC
/FrequencyConsumption
(V
CC
= 5 V ± 10%)
0
10
20
30
40
60
70
80
90
100
110
V
CC
= 5V
50
0
10
15
5
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
I
C
TURBO ON (100%)
TURBO ON (25%)
TURBOOFF
TURBO OFF
PT 100%
PT 25%
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
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