參數(shù)資料
型號(hào): PSD913F2
英文描述: 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述: 可配置的存儲(chǔ)系統(tǒng)級(jí)芯片的8位微控制器
文件頁(yè)數(shù): 38/94頁(yè)
文件大?。?/td> 463K
代理商: PSD913F2
Preliminary
PSD913F1
37
The
PSD913F1
Functional
Blocks
(cont.)
9.3 Microcontroller Bus Interface
The
no-glue logic
PSD913F1 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 15. The interface type is specified using
the PSDsoft.
Data
Bus
Width
MCU
CNTL0
CNTL1
CNTL2
PC7
*
*
*
*
*
*
*
DBE
*
*
*
*
PD0**
ADIO0
PA3-PA0 PA7-PA4
*
A3-A0
*
*
*
*
*
*
D3-D0
*
*
D3-D0
8031/8051
80C51XA
80C251
80C251
80198
68HC11
68HC05C0
68HC912
Z80
Z8
68330
M37702M2
8
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
WR
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
RD
E
RD
DS
DS
E
PSEN
PSEN
*
PSEN
*
*
*
*
*
*
*
*
ALE
ALE
ALE
ALE
ALE
AS
AS
AS
*
AS
AS
ALE
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
*
D7-D4
*
*
D7-D4
Table 15. Microcontrollers and their Control Signals
*
*
Unused CNTL2 pin can be configured as PLD input. Other unused pins (PC7, PD0, PA3-0) can be
**
configured for other I/O functions.
**
ALE/AS input is optional for microcontrollers with a non-multiplexed bus
9.3.1. PSD913F1 Interface to a Multiplexed 8-Bit Bus
Figure 14 shows an example of a system using a microcontroller with an 8-bit multiplexed
bus and a PSD913F1. The ADIO port on the PSD913F1 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port A or B. The PSD913F1 drives the ADIO data bus only
when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional
address inputs.
9.3.2. PSD913F1 Interface to a Non-Multiplexed 8-Bit Bus
Figure 15 shows an example of a system using a microcontroller with an 8-bit
non-multiplexed bus and a PSD913F1. The address bus is connected to the ADIO Port, and
the data bus is connected to Port A. Port A is in tri-state mode when the PSD913F1 is not
accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports
B, C, or D may be used for additional address inputs.
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
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