參數(shù)資料
型號(hào)： PSD913F2
英文描述： 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述： 可配置的存儲(chǔ)系統(tǒng)級(jí)芯片的8位微控制器
文件頁(yè)數(shù)： 36/94頁(yè)
文件大?。?/td> 463K
代理商： PSD913F2
Preliminary
PSD913F1
35
The
PSD913F1
Functional
Blocks
(cont.)
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 12, is used for decoding the address for internal PSD
components. The DPLD can generate the following chip selects:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the Secondary Flash memory (three product terms each)
1 internal SRAM select (two product terms)
1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and
other user defined external inputs from Ports A, B, C or D.
9.2.2 General Purpose PLD (GPLD)
The General Purpose PLD implements user defined system combinatorial logic function
or chip selects for external devices. Figure 13 shows how the GPLD is connected to the I/O
Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can also be
configured as input tot eh GPLD. When it is not used as GPLD output or input, the pin can
be configured to perform other I/O functions.
The GPLD outputs are identical except in the number of available product terms for logic
implementation. Select the pin that can best meet the product term requirement of your
logic function or chip selects. The outputs can be configured as active high or low outputs.
Table 14 shows the number of product terms that are assigned to the PLD outputs on the
I/O Ports. When PSD913F1 is connected to a MCU with non-multiplexed bus, Port A will be
configured as the Data Port and the GPLD outputs will not be available.
GPLD Output on Port Pin
Number of Product Terms
Port A, pins PA0-3
Port A, pins PA4-7
Port B, pins PB0-3
Port B, pins PB4-7
Port D, pins PD0-2
3
9
4
7
1
Table 14. GPLD Output Product Term
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F2-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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