參數(shù)資料
型號: PSD913F2
英文描述: 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述: 可配置的存儲系統(tǒng)級芯片的8位微控制器
文件頁數(shù): 32/94頁
文件大小: 463K
代理商: PSD913F2
Preliminary
PSD913F1
31
The
PSD913F1
Functional
Blocks
(cont.)
FLASH
DPLD
EEPROM
SRAM
RS0
EES0-3
FS0-7
CS
CS
CS
OE
OE
RD
PSEN
OE
Figure 8. 8031 Memory Modes – Separate Space Mode
FLASH
DPLD
EEPROM
SRAM
RS0
EES0-3
FS0-7
RD
CS
CS
CS
RD
OE
OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
Figure 9. 80C31 Memory Mode – Combined Space Mode
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the Flash Memory, while the RD signal is
used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires
the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example,
to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM
register are set to
1
.
9.1.3.3 80C31 Memory Map Example
See Application Notes for examples.
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
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