參數(shù)資料
型號(hào)： PSD913F2
英文描述： 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述： 可配置的存儲(chǔ)系統(tǒng)級(jí)芯片的8位微控制器
文件頁數(shù)： 24/94頁
文件大?。?/td> 463K
代理商： PSD913F2
Preliminary
PSD913F1
23
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
Page Write
Instruction
SDP is set
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
WRITE Data to
be Written in
any Address
Page Write
Instruction
SDP
Set
SDP
not Set
Write
in Memory
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
WRITE
is enabled
SDP ENABLE ALGORITHM
Figure 3. EEPROM SDP Enable Flowcharts
The
PSD913F1
Functional
Blocks
(cont.)
9.1.1.6.3 EEPROM Software Data Protect (SDP)
(cont.)
To enable SDP mode at run time, the MCU must write three specific data bytes at three
specific memory locations, as shown in Figure 3. Any further writes to EEPROM when SDP
is set will require this same sequence, followed by the byte(s) to write. The first SDP enable
sequence can be followed directly by the byte(s) to be written.
To disable SDP mode, the MCU must write specific bytes to six specific locations, as shown
in Figure 4.
The MCU must not be executing code from EEPROM when these instructions are invoked.
The MCU must be operating from some other memory when enabling or disabling SDP
mode.
The state of SDP mode is not changed by power on/off sequences (nonvolatile). When
either the SDP enable or SDP disable instructions are issued from the MCU, the MCU must
use the Toggle bit (status bit DQ6) or the Ready/Busy output pin to check programming
status. The Ready/Busy output is driven low from the first write of AAh @ 555h until the
completion of the internal storage sequence. Data Polling (status bit DQ7) is not supported
when issuing the SDP enable or SDP disable commands.
Note:
Using the SDP sequence (enabling, disabling, or writing data) is initiated when
specific bytes are written to addresses on specific
“
pages
”
of EEPROM memory, with no
more than 120 μsec between writes. The addresses 555h and AAAh are located on
different pages of EEPROM. This is how the PSD913F1 distinguishes these instruction
sequences from ordinary writes to EEPROM, which are expected to be within a single
EEPROM page.
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F2-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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